From: "Marek Behún" <kabel@kernel.org>
To: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: pali@kernel.org, linux-pci@vger.kernel.org,
"Marek Behún" <kabel@kernel.org>
Subject: [PATCH v3 02/11] PCI: pci-bridge-emul: Add definitions for missing capabilities registers
Date: Tue, 30 Nov 2021 14:25:14 +0100 [thread overview]
Message-ID: <20211130132523.28126-3-kabel@kernel.org> (raw)
In-Reply-To: <20211130132523.28126-1-kabel@kernel.org>
From: Pali Rohár <pali@kernel.org>
pci-bridge-emul driver already allocates buffer for capabilities up to the
PCI_EXP_SLTSTA2 register, but does not define bit access behavior for these
registers. Add these missing definitions.
Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Marek Behún <kabel@kernel.org>
---
Changes since v2:
- updated definitions of registers PCI_EXP_DEVCAP2 and PCI_EXP_DEVCTL2
---
drivers/pci/pci-bridge-emul.c | 43 +++++++++++++++++++++++++++++++++++
1 file changed, 43 insertions(+)
diff --git a/drivers/pci/pci-bridge-emul.c b/drivers/pci/pci-bridge-emul.c
index a4af1a533d71..0d1177e52a43 100644
--- a/drivers/pci/pci-bridge-emul.c
+++ b/drivers/pci/pci-bridge-emul.c
@@ -251,6 +251,49 @@ struct pci_bridge_reg_behavior pcie_cap_regs_behavior[PCI_CAP_PCIE_SIZEOF / 4] =
.ro = GENMASK(15, 0) | PCI_EXP_RTSTA_PENDING,
.w1c = PCI_EXP_RTSTA_PME,
},
+
+ [PCI_EXP_DEVCAP2 / 4] = {
+ /*
+ * Device capabilities 2 register has reserved bits [30:27].
+ * Also bits [26:24] are reserved for non-upstream ports.
+ */
+ .ro = BIT(31) | GENMASK(23, 0),
+ },
+
+ [PCI_EXP_DEVCTL2 / 4] = {
+ /*
+ * Device control 2 register is RW. Bit 11 is reserved for
+ * non-upstream ports.
+ *
+ * Device status 2 register is reserved.
+ */
+ .rw = GENMASK(15, 12) | GENMASK(10, 0),
+ },
+
+ [PCI_EXP_LNKCAP2 / 4] = {
+ /* Link capabilities 2 register has reserved bits [30:25] and 0. */
+ .ro = BIT(31) | GENMASK(24, 1),
+ },
+
+ [PCI_EXP_LNKCTL2 / 4] = {
+ /*
+ * Link control 2 register is RW.
+ *
+ * Link status 2 register has bits 5, 15 W1C;
+ * bits 10, 11 reserved and others are RO.
+ */
+ .rw = GENMASK(15, 0),
+ .w1c = (BIT(15) | BIT(5)) << 16,
+ .ro = (GENMASK(14, 12) | GENMASK(9, 6) | GENMASK(4, 0)) << 16,
+ },
+
+ [PCI_EXP_SLTCAP2 / 4] = {
+ /* Slot capabilities 2 register is reserved. */
+ },
+
+ [PCI_EXP_SLTCTL2 / 4] = {
+ /* Both Slot control 2 and Slot status 2 registers are reserved. */
+ },
};
/*
--
2.32.0
next prev parent reply other threads:[~2021-11-30 13:25 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-30 13:25 [PATCH v3 00/11] PCI: aardvark controller fixes BATCH 3 Marek Behún
2021-11-30 13:25 ` [PATCH v3 01/11] PCI: pci-bridge-emul: Add description for class_revision field Marek Behún
2021-11-30 13:25 ` Marek Behún [this message]
2021-11-30 13:25 ` [PATCH v3 03/11] PCI: aardvark: Add support for DEVCAP2, DEVCTL2, LNKCAP2 and LNKCTL2 registers on emulated bridge Marek Behún
2021-11-30 13:25 ` [PATCH v3 04/11] PCI: aardvark: Clear all MSIs at setup Marek Behún
2021-11-30 13:25 ` [PATCH v3 05/11] PCI: aardvark: Comment actions in driver remove method Marek Behún
2021-11-30 13:25 ` [PATCH v3 06/11] PCI: aardvark: Disable bus mastering when unbinding driver Marek Behún
2021-11-30 13:25 ` [PATCH v3 07/11] PCI: aardvark: Mask all interrupts " Marek Behún
2021-11-30 13:25 ` [PATCH v3 08/11] PCI: aardvark: Fix memory leak in driver unbind Marek Behún
2021-11-30 13:25 ` [PATCH v3 09/11] PCI: aardvark: Assert PERST# when unbinding driver Marek Behún
2021-11-30 13:25 ` [PATCH v3 10/11] PCI: aardvark: Disable link training " Marek Behún
2021-11-30 13:25 ` [PATCH v3 11/11] PCI: aardvark: Disable common PHY " Marek Behún
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