Re: [RESEND PATCH v2] PCI: mediatek: Delay 100ms to wait power and clock to become stable

Bjorn Helgaas
2021-12-07T17:54:23Z

[+cc Marc, Alyssa, Mark, Luca for reset timing questions]

On Tue, Dec 07, 2021 at 04:41:53PM +0800, qizhong cheng wrote:
> Described in PCIe CEM specification sections 2.2 (PERST# Signal) and
> 2.2.1 (Initial Power-Up (G3 to S0)). The deassertion of PERST# should
> be delayed 100ms (TPVPERL) for the power and clock to become stable.
>
> Signed-off-by: qizhong cheng <qizhong.cheng@mediatek.com>
> Acked-by: Pali Rohár <pali@kernel.org>
> ---
>
> v2:
> - Typo fix.
> - Rewrap into one paragraph.

1) If you change something, even in the commit log or comments, it is
a new version, not a "RESEND". A "RESEND" means "I sent this quite a
while ago and didn't hear anything, so I'm sending the exact same
thing again in case the first one got lost."

2) I suggested a subject line update, which apparently got missed.
Here's a better one:

PCI: mediatek: Assert PERST# for 100ms for power and clock to stabilize

3) Most importantly, this needs to be reconciled with the similar
change to the apple driver:

https://lore.kernel.org/r/20211123180636.80558-2-maz@kernel.org

In the apple driver, we're doing:

- Assert PERST#
- Set up REFCLK
- Sleep 100us (T_perst-clk, CEM r5 2.2, 2.9.2)
- Deassert PERST#
- Sleep 100ms (not sure there's a name? PCIe r5 6.6.1)

But here in mediatek, we're doing:

- Assert PERST#
- Sleep 100ms (T_pvperl, CEM r5 2.2, 2.2.1, 2.9.2)
- Deassert PERST#

My questions:

- Where does apple enforce T_pvperl? I can't tell where power to
the slot is turned on.

- Where does mediatek enforce the PCIe sec 6.6.1 delay after
deasserting PERST# and before config requests?

- Does either apple or mediatek support speeds greater than 5 GT/s,
and if so, shouldn't we start the sec 6.6.1 100ms delay *after*
Link training completes?

> drivers/pci/controller/pcie-mediatek.c | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/drivers/pci/controller/pcie-mediatek.c b/drivers/pci/controller/pcie-mediatek.c
> index 2f3f974977a3..a61ea3940471 100644
> --- a/drivers/pci/controller/pcie-mediatek.c
> +++ b/drivers/pci/controller/pcie-mediatek.c
> @@ -702,6 +702,13 @@ static int mtk_pcie_startup_port_v2(struct mtk_pcie_port *port)
> */
> writel(PCIE_LINKDOWN_RST_EN, port->base + PCIE_RST_CTRL);
>
> + /*
> + * Described in PCIe CEM specification sections 2.2 (PERST# Signal) and
> + * 2.2.1 (Initial Power-Up (G3 to S0)). The deassertion of PERST# should
> + * be delayed 100ms (TPVPERL) for the power and clock to become stable.
> + */
> + msleep(100);
> +
> /* De-assert PHY, PE, PIPE, MAC and configuration reset */
> val = readl(port->base + PCIE_RST_CTRL);
> val |= PCIE_PHY_RSTB | PCIE_PERSTB | PCIE_PIPE_SRSTB |
> --
> 2.25.1
>