From: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
To: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Cc: "Andy Gross" <agross@kernel.org>,
"Bjorn Andersson" <bjorn.andersson@linaro.org>,
"Rob Herring" <robh+dt@kernel.org>,
"Vinod Koul" <vkoul@kernel.org>,
"Kishon Vijay Abraham I" <kishon@ti.com>,
"Stanimir Varbanov" <svarbanov@mm-sol.com>,
"Lorenzo Pieralisi" <lorenzo.pieralisi@arm.com>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Krzysztof Wilczyński" <kw@linux.com>,
linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org,
devicetree@vger.kernel.org, linux-phy@lists.infradead.org
Subject: Re: [PATCH v2 04/10] PCI: qcom: Remove redundancy between qcom_pcie and qcom_pcie_cfg
Date: Fri, 10 Dec 2021 16:45:41 +0530 [thread overview]
Message-ID: <20211210111541.GD1734@thinkpad> (raw)
In-Reply-To: <20211208171442.1327689-5-dmitry.baryshkov@linaro.org>
On Wed, Dec 08, 2021 at 08:14:36PM +0300, Dmitry Baryshkov wrote:
> In preparation to adding more flags to configuration data, use struct
> qcom_pcie_cfg directly inside struct qcom_pcie, rather than duplicating
> all its fields. This would save us from the boilerplate code that just
> copies flags values from one sruct to another one.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
> drivers/pci/controller/dwc/pcie-qcom.c | 39 +++++++++++---------------
> 1 file changed, 17 insertions(+), 22 deletions(-)
>
> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
> index 1c3d1116bb60..51a0475173fb 100644
> --- a/drivers/pci/controller/dwc/pcie-qcom.c
> +++ b/drivers/pci/controller/dwc/pcie-qcom.c
> @@ -204,8 +204,7 @@ struct qcom_pcie {
> union qcom_pcie_resources res;
> struct phy *phy;
> struct gpio_desc *reset;
> - const struct qcom_pcie_ops *ops;
> - unsigned int pipe_clk_need_muxing:1;
> + const struct qcom_pcie_cfg *cfg;
There is no change in this patch that adds "pipe_clk_need_muxing" to
qcom_pcie_cfg.
Thanks,
Mani
> };
>
> #define to_qcom_pcie(x) dev_get_drvdata((x)->dev)
> @@ -229,8 +228,8 @@ static int qcom_pcie_start_link(struct dw_pcie *pci)
> struct qcom_pcie *pcie = to_qcom_pcie(pci);
>
> /* Enable Link Training state machine */
> - if (pcie->ops->ltssm_enable)
> - pcie->ops->ltssm_enable(pcie);
> + if (pcie->cfg->ops->ltssm_enable)
> + pcie->cfg->ops->ltssm_enable(pcie);
>
> return 0;
> }
> @@ -1176,7 +1175,7 @@ static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie)
> if (ret < 0)
> return ret;
>
> - if (pcie->pipe_clk_need_muxing) {
> + if (pcie->cfg->pipe_clk_need_muxing) {
> res->pipe_clk_src = devm_clk_get(dev, "pipe_mux");
> if (IS_ERR(res->pipe_clk_src))
> return PTR_ERR(res->pipe_clk_src);
> @@ -1209,7 +1208,7 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie)
> }
>
> /* Set TCXO as clock source for pcie_pipe_clk_src */
> - if (pcie->pipe_clk_need_muxing)
> + if (pcie->cfg->pipe_clk_need_muxing)
> clk_set_parent(res->pipe_clk_src, res->ref_clk_src);
>
> ret = clk_bulk_prepare_enable(res->num_clks, res->clks);
> @@ -1284,7 +1283,7 @@ static int qcom_pcie_post_init_2_7_0(struct qcom_pcie *pcie)
> struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0;
>
> /* Set pipe clock as clock source for pcie_pipe_clk_src */
> - if (pcie->pipe_clk_need_muxing)
> + if (pcie->cfg->pipe_clk_need_muxing)
> clk_set_parent(res->pipe_clk_src, res->phy_pipe_clk);
>
> return clk_prepare_enable(res->pipe_clk);
> @@ -1384,7 +1383,7 @@ static int qcom_pcie_host_init(struct pcie_port *pp)
>
> qcom_ep_reset_assert(pcie);
>
> - ret = pcie->ops->init(pcie);
> + ret = pcie->cfg->ops->init(pcie);
> if (ret)
> return ret;
>
> @@ -1392,16 +1391,16 @@ static int qcom_pcie_host_init(struct pcie_port *pp)
> if (ret)
> goto err_deinit;
>
> - if (pcie->ops->post_init) {
> - ret = pcie->ops->post_init(pcie);
> + if (pcie->cfg->ops->post_init) {
> + ret = pcie->cfg->ops->post_init(pcie);
> if (ret)
> goto err_disable_phy;
> }
>
> qcom_ep_reset_deassert(pcie);
>
> - if (pcie->ops->config_sid) {
> - ret = pcie->ops->config_sid(pcie);
> + if (pcie->cfg->ops->config_sid) {
> + ret = pcie->cfg->ops->config_sid(pcie);
> if (ret)
> goto err;
> }
> @@ -1410,12 +1409,12 @@ static int qcom_pcie_host_init(struct pcie_port *pp)
>
> err:
> qcom_ep_reset_assert(pcie);
> - if (pcie->ops->post_deinit)
> - pcie->ops->post_deinit(pcie);
> + if (pcie->cfg->ops->post_deinit)
> + pcie->cfg->ops->post_deinit(pcie);
> err_disable_phy:
> phy_power_off(pcie->phy);
> err_deinit:
> - pcie->ops->deinit(pcie);
> + pcie->cfg->ops->deinit(pcie);
>
> return ret;
> }
> @@ -1531,7 +1530,6 @@ static int qcom_pcie_probe(struct platform_device *pdev)
> struct pcie_port *pp;
> struct dw_pcie *pci;
> struct qcom_pcie *pcie;
> - const struct qcom_pcie_cfg *pcie_cfg;
> int ret;
>
> pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
> @@ -1553,15 +1551,12 @@ static int qcom_pcie_probe(struct platform_device *pdev)
>
> pcie->pci = pci;
>
> - pcie_cfg = of_device_get_match_data(dev);
> - if (!pcie_cfg || !pcie_cfg->ops) {
> + pcie->cfg = of_device_get_match_data(dev);
> + if (!pcie->cfg || !pcie->cfg->ops) {
> dev_err(dev, "Invalid platform data\n");
> return -EINVAL;
> }
>
> - pcie->ops = pcie_cfg->ops;
> - pcie->pipe_clk_need_muxing = pcie_cfg->pipe_clk_need_muxing;
> -
> pcie->reset = devm_gpiod_get_optional(dev, "perst", GPIOD_OUT_HIGH);
> if (IS_ERR(pcie->reset)) {
> ret = PTR_ERR(pcie->reset);
> @@ -1586,7 +1581,7 @@ static int qcom_pcie_probe(struct platform_device *pdev)
> goto err_pm_runtime_put;
> }
>
> - ret = pcie->ops->get_resources(pcie);
> + ret = pcie->cfg->ops->get_resources(pcie);
> if (ret)
> goto err_pm_runtime_put;
>
> --
> 2.33.0
>
next prev parent reply other threads:[~2021-12-10 11:15 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-12-08 17:14 [PATCH v2 00/10] qcom: add support for PCIe0 on SM8450 platform Dmitry Baryshkov
2021-12-08 17:14 ` [PATCH v2 01/10] dt-bindings: pci: qcom: Document PCIe bindings for SM8450 Dmitry Baryshkov
2021-12-10 8:42 ` Manivannan Sadhasivam
2021-12-08 17:14 ` [PATCH v2 02/10] dt-bindings: phy: qcom,qmp: Add SM8450 PCIe PHY bindings Dmitry Baryshkov
2021-12-08 17:14 ` [PATCH v2 03/10] phy: qcom-qmp: Add SM8450 PCIe0 PHY support Dmitry Baryshkov
2021-12-08 17:14 ` [PATCH v2 04/10] PCI: qcom: Remove redundancy between qcom_pcie and qcom_pcie_cfg Dmitry Baryshkov
2021-12-10 11:15 ` Manivannan Sadhasivam [this message]
2021-12-11 1:56 ` Dmitry Baryshkov
2021-12-08 17:14 ` [PATCH v2 05/10] PCI: qcom: Add ddrss_sf_tbu flag Dmitry Baryshkov
2021-12-10 11:22 ` Manivannan Sadhasivam
2021-12-11 1:59 ` Dmitry Baryshkov
2021-12-11 3:11 ` Manivannan Sadhasivam
2021-12-08 17:14 ` [PATCH v2 06/10] PCI: qcom: Add SM8450 PCIe support Dmitry Baryshkov
2021-12-10 11:30 ` Manivannan Sadhasivam
2021-12-11 2:01 ` Dmitry Baryshkov
2021-12-11 3:07 ` Manivannan Sadhasivam
2021-12-08 17:14 ` [PATCH v2 07/10] arm64: dts: qcom: sm8450: add PCIe0 PHY node Dmitry Baryshkov
2021-12-10 11:37 ` Manivannan Sadhasivam
2021-12-11 2:10 ` Dmitry Baryshkov
2021-12-08 17:14 ` [PATCH v2 08/10] arm64: dts: qcom: sm8450: add PCIe0 RC device Dmitry Baryshkov
2021-12-10 12:06 ` Manivannan Sadhasivam
2021-12-11 2:24 ` Dmitry Baryshkov
2021-12-12 21:34 ` Rob Herring
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