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From: Jonathan Cameron <Jonathan.Cameron@Huawei.com>
To: Dan Williams <dan.j.williams@intel.com>
Cc: <linux-cxl@vger.kernel.org>, <linux-pci@vger.kernel.org>,
	<nvdimm@lists.linux.dev>
Subject: Re: [PATCH v3 15/40] cxl: Prove CXL locking
Date: Mon, 31 Jan 2022 15:48:48 +0000	[thread overview]
Message-ID: <20220131154848.00006615@Huawei.com> (raw)
In-Reply-To: <164298419875.3018233.7880727408723281411.stgit@dwillia2-desk3.amr.corp.intel.com>

On Sun, 23 Jan 2022 16:29:58 -0800
Dan Williams <dan.j.williams@intel.com> wrote:

> When CONFIG_PROVE_LOCKING is enabled the 'struct device' definition gets
> an additional mutex that is not clobbered by
> lockdep_set_novalidate_class() like the typical device_lock(). This
> allows for local annotation of subsystem locks with mutex_lock_nested()
> per the subsystem's object/lock hierarchy. For CXL, this primarily needs
> the ability to lock ports by depth and child objects of ports by their
> parent parent-port lock.
> 
> Signed-off-by: Dan Williams <dan.j.williams@intel.com>

Hi Dan,

This infrastructure is nice.

A few comments inline - mostly requests for a few comments to make
life easier when reading this in future.  Also, I'd slightly prefer
this as 2 patches so the trivial nvdimm / Kconfig.debug stuff is separate
from the patch actually introducing support for this in CXL.

Anyhow, all trivial stuff so as far as I'm concerned.

Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>

Thanks,

Jonathan

> ---
>  drivers/cxl/acpi.c       |   10 +++---
>  drivers/cxl/core/pmem.c  |    4 +-
>  drivers/cxl/core/port.c  |   43 ++++++++++++++++++++-------
>  drivers/cxl/cxl.h        |   74 ++++++++++++++++++++++++++++++++++++++++++++++
>  drivers/cxl/pmem.c       |   12 ++++---
>  drivers/nvdimm/nd-core.h |    2 +
>  lib/Kconfig.debug        |   23 ++++++++++++++
>  7 files changed, 143 insertions(+), 25 deletions(-)
> 


> @@ -712,15 +725,23 @@ static int cxl_bus_match(struct device *dev, struct device_driver *drv)
>  
>  static int cxl_bus_probe(struct device *dev)
>  {
> -	return to_cxl_drv(dev->driver)->probe(dev);
> +	int rc;
> +
> +	cxl_nested_lock(dev);

I guess it is 'fairly' obvious why this call is here (I assume because the device
lock is already held), but maybe worth a comment?

> +	rc = to_cxl_drv(dev->driver)->probe(dev);
> +	cxl_nested_unlock(dev);
> +
> +	return rc;
>  }
>  
>  static void cxl_bus_remove(struct device *dev)
>  {
>  	struct cxl_driver *cxl_drv = to_cxl_drv(dev->driver);
>  
> +	cxl_nested_lock(dev);
>  	if (cxl_drv->remove)
>  		cxl_drv->remove(dev);
> +	cxl_nested_unlock(dev);
>  }
>  
>  struct bus_type cxl_bus_type = {
> diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
> index c1dc53492773..569cbe7f23d6 100644
> --- a/drivers/cxl/cxl.h
> +++ b/drivers/cxl/cxl.h
> @@ -285,6 +285,7 @@ static inline bool is_cxl_root(struct cxl_port *port)
>  	return port->uport == port->dev.parent;
>  }
>  
> +bool is_cxl_port(struct device *dev);
>  struct cxl_port *to_cxl_port(struct device *dev);
>  struct cxl_port *devm_cxl_add_port(struct device *host, struct device *uport,
>  				   resource_size_t component_reg_phys,
> @@ -295,6 +296,7 @@ int cxl_add_dport(struct cxl_port *port, struct device *dport, int port_id,
>  
>  struct cxl_decoder *to_cxl_decoder(struct device *dev);
>  bool is_root_decoder(struct device *dev);
> +bool is_cxl_decoder(struct device *dev);
>  struct cxl_decoder *cxl_root_decoder_alloc(struct cxl_port *port,
>  					   unsigned int nr_targets);
>  struct cxl_decoder *cxl_switch_decoder_alloc(struct cxl_port *port,
> @@ -347,4 +349,76 @@ struct cxl_nvdimm_bridge *cxl_find_nvdimm_bridge(struct cxl_nvdimm *cxl_nvd);
>  #ifndef __mock
>  #define __mock static
>  #endif
> +
> +#ifdef CONFIG_PROVE_CXL_LOCKING
> +enum cxl_lock_class {
> +	CXL_ANON_LOCK,
> +	CXL_NVDIMM_LOCK,
> +	CXL_NVDIMM_BRIDGE_LOCK,
> +	CXL_PORT_LOCK,

As you are going to increment off the end of this perhaps a comment
here so that no one thinks "I'll just add another entry after CXL_PORT_LOCK"

> +};
> +
> +static inline void cxl_nested_lock(struct device *dev)
> +{
> +	if (is_cxl_port(dev)) {
> +		struct cxl_port *port = to_cxl_port(dev);
> +
> +		mutex_lock_nested(&dev->lockdep_mutex,
> +				  CXL_PORT_LOCK + port->depth);
> +	} else if (is_cxl_decoder(dev)) {
> +		struct cxl_port *port = to_cxl_port(dev->parent);
> +
> +		mutex_lock_nested(&dev->lockdep_mutex,
> +				  CXL_PORT_LOCK + port->depth + 1);

Perhaps a comment on why port->dev + 1 is a safe choice?
Not immediately obvious to me and I'm too lazy to figure it out :)

> +	} else if (is_cxl_nvdimm_bridge(dev))
> +		mutex_lock_nested(&dev->lockdep_mutex, CXL_NVDIMM_BRIDGE_LOCK);
> +	else if (is_cxl_nvdimm(dev))
> +		mutex_lock_nested(&dev->lockdep_mutex, CXL_NVDIMM_LOCK);
> +	else
> +		mutex_lock_nested(&dev->lockdep_mutex, CXL_ANON_LOCK);
> +}
> +
> +static inline void cxl_nested_unlock(struct device *dev)
> +{
> +	mutex_unlock(&dev->lockdep_mutex);
> +}
> +
> +static inline void cxl_device_lock(struct device *dev)
> +{
> +	/*
> +	 * For double lock errors the lockup will happen before lockdep
> +	 * warns at cxl_nested_lock(), so assert explicitly.
> +	 */
> +	lockdep_assert_not_held(&dev->lockdep_mutex);
> +
> +	device_lock(dev);
> +	cxl_nested_lock(dev);
> +}
> +
> +static inline void cxl_device_unlock(struct device *dev)
> +{
> +	cxl_nested_unlock(dev);
> +	device_unlock(dev);
> +}
> +#else
> +static inline void cxl_nested_lock(struct device *dev)
> +{
> +}
> +
> +static inline void cxl_nested_unlock(struct device *dev)
> +{
> +}
> +
> +static inline void cxl_device_lock(struct device *dev)
> +{
> +	device_lock(dev);
> +}
> +
> +static inline void cxl_device_unlock(struct device *dev)
> +{
> +	device_unlock(dev);
> +}
> +#endif
> +
> +

One blank line only.

>  #endif /* __CXL_H__ */
...
> diff --git a/drivers/nvdimm/nd-core.h b/drivers/nvdimm/nd-core.h
> index a11850dd475d..2650a852eeaf 100644
> --- a/drivers/nvdimm/nd-core.h
> +++ b/drivers/nvdimm/nd-core.h
> @@ -185,7 +185,7 @@ static inline void devm_nsio_disable(struct device *dev,
>  }
>  #endif
>  
> -#ifdef CONFIG_PROVE_LOCKING
> +#ifdef CONFIG_PROVE_NVDIMM_LOCKING
>  extern struct class *nd_class;
>  
>  enum {
> diff --git a/lib/Kconfig.debug b/lib/Kconfig.debug
> index 9ef7ce18b4f5..ea9291723d06 100644
> --- a/lib/Kconfig.debug
> +++ b/lib/Kconfig.debug
> @@ -1509,6 +1509,29 @@ config CSD_LOCK_WAIT_DEBUG
>  	  include the IPI handler function currently executing (if any)
>  	  and relevant stack traces.
>  
> +choice
> +	prompt "Lock debugging: prove subsystem device_lock() correctness"
> +	depends on PROVE_LOCKING
> +	help
> +	  For subsystems that have instrumented their usage of the device_lock()
> +	  with nested annotations, enable lock dependency checking. The locking
> +	  hierarchy 'subclass' identifiers are not compatible across
> +	  sub-systems, so only one can be enabled at a time.
> +
> +config PROVE_NVDIMM_LOCKING
> +	bool "NVDIMM"
> +	depends on LIBNVDIMM
> +	help
> +	  Enable lockdep to validate nd_device_lock() usage.

I would slightly have preferred a first patch that pulled out the NVDIMM parts
and a second that introduced it for CXL.

> +
> +config PROVE_CXL_LOCKING
> +	bool "CXL"
> +	depends on CXL_BUS
> +	help
> +	  Enable lockdep to validate cxl_device_lock() usage.
> +
> +endchoice
> +
>  endmenu # lock debugging
>  
>  config TRACE_IRQFLAGS
> 


  reply	other threads:[~2022-01-31 15:49 UTC|newest]

Thread overview: 172+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-01-24  0:28 [PATCH v3 00/40] CXL.mem Topology Discovery and Hotplug Support Dan Williams
2022-01-24  0:28 ` [PATCH v3 01/40] cxl: Rename CXL_MEM to CXL_PCI Dan Williams
2022-01-24  0:28 ` [PATCH v3 02/40] cxl/pci: Implement Interface Ready Timeout Dan Williams
2022-01-31 22:21   ` Ben Widawsky
2022-01-31 23:11     ` Dan Williams
2022-01-31 23:25       ` Ben Widawsky
2022-01-31 23:47         ` Dan Williams
2022-01-31 23:51   ` [PATCH v4 " Dan Williams
2022-01-24  0:28 ` [PATCH v3 03/40] cxl/pci: Defer mailbox status checks to command timeouts Dan Williams
2022-01-31 22:28   ` Ben Widawsky
2022-01-24  0:29 ` [PATCH v3 04/40] cxl: Flesh out register names Dan Williams
2022-01-24  0:29 ` [PATCH v3 05/40] cxl/pci: Add new DVSEC definitions Dan Williams
2022-01-24  0:29 ` [PATCH v3 06/40] cxl/acpi: Map component registers for Root Ports Dan Williams
2022-01-24  0:29 ` [PATCH v3 07/40] cxl: Introduce module_cxl_driver Dan Williams
2022-01-24  0:29 ` [PATCH v3 08/40] cxl/core/port: Rename bus.c to port.c Dan Williams
2022-01-31 22:34   ` Ben Widawsky
2022-01-24  0:29 ` [PATCH v3 09/40] cxl/decoder: Hide physical address information from non-root Dan Williams
2022-01-31 14:14   ` Jonathan Cameron
2022-01-31 22:34   ` Ben Widawsky
2022-01-24  0:29 ` [PATCH v3 10/40] cxl/core: Convert decoder range to resource Dan Williams
2022-01-24  0:29 ` [PATCH v3 11/40] cxl/core/port: Clarify decoder creation Dan Williams
2022-01-31 14:46   ` Jonathan Cameron
2022-01-31 21:17     ` Dan Williams
2022-01-31 21:33   ` [PATCH v4 " Dan Williams
2022-02-01 10:49     ` Jonathan Cameron
2022-01-24  0:29 ` [PATCH v3 12/40] cxl/core: Fix cxl_probe_component_regs() error message Dan Williams
2022-01-31 14:53   ` Jonathan Cameron
2022-01-31 22:29     ` Dan Williams
2022-01-31 22:39   ` Ben Widawsky
2022-01-24  0:29 ` [PATCH v3 13/40] cxl/core/port: Make passthrough decoder init implicit Dan Williams
2022-01-31 14:56   ` Jonathan Cameron
2022-01-24  0:29 ` [PATCH v3 14/40] cxl/core: Track port depth Dan Williams
2022-01-31 14:57   ` Jonathan Cameron
2022-01-24  0:29 ` [PATCH v3 15/40] cxl: Prove CXL locking Dan Williams
2022-01-31 15:48   ` Jonathan Cameron [this message]
2022-01-31 19:43     ` Dan Williams
2022-01-31 19:50   ` [PATCH v4 " Dan Williams
2022-01-31 23:23     ` Ben Widawsky
2022-01-24  0:30 ` [PATCH v3 16/40] cxl/core/port: Use dedicated lock for decoder target list Dan Williams
2022-01-26  2:54   ` [PATCH v4 " Dan Williams
2022-01-31 15:59     ` Jonathan Cameron
2022-01-31 23:31       ` Dan Williams
2022-01-31 23:34     ` Ben Widawsky
2022-01-31 23:38       ` Dan Williams
2022-01-31 23:42         ` Ben Widawsky
2022-01-31 23:58           ` Dan Williams
2022-01-31 23:35     ` [PATCH v5 " Dan Williams
2022-02-01 10:52       ` Jonathan Cameron
2022-01-24  0:30 ` [PATCH v3 17/40] cxl/port: Introduce cxl_port_to_pci_bus() Dan Williams
2022-01-31 16:04   ` Jonathan Cameron
2022-01-31 16:44   ` [PATCH v4 " Dan Williams
2022-01-31 23:41     ` Ben Widawsky
2022-01-24  0:30 ` [PATCH v3 18/40] cxl/pmem: Introduce a find_cxl_root() helper Dan Williams
2022-01-26 18:55   ` [PATCH v4 " Dan Williams
2022-01-26 23:59     ` [PATCH v5 " Dan Williams
2022-01-31 16:18       ` Jonathan Cameron
2022-02-01  0:22         ` Dan Williams
2022-02-01 10:58           ` Jonathan Cameron
2022-02-01  0:34       ` [PATCH v6 " Dan Williams
2022-02-01 10:59         ` Jonathan Cameron
2022-01-24  0:30 ` [PATCH v3 19/40] cxl/port: Up-level cxl_add_dport() locking requirements to the caller Dan Williams
2022-01-31 16:20   ` Jonathan Cameron
2022-01-31 23:47   ` Ben Widawsky
2022-02-01  0:43     ` Dan Williams
2022-02-01  1:07   ` [PATCH v4 " Dan Williams
2022-02-01 11:00     ` Jonathan Cameron
2022-01-24  0:30 ` [PATCH v3 20/40] cxl/pci: Rename pci.h to cxlpci.h Dan Williams
2022-01-31 16:22   ` Jonathan Cameron
2022-02-01  0:00     ` Dan Williams
2022-01-31 23:48   ` Ben Widawsky
2022-01-24  0:30 ` [PATCH v3 21/40] cxl/core: Generalize dport enumeration in the core Dan Williams
2022-01-31 17:02   ` Jonathan Cameron
2022-02-01  1:58     ` Dan Williams
2022-02-01  2:10   ` [PATCH v4 " Dan Williams
2022-02-01 11:03     ` Jonathan Cameron
2022-01-24  0:30 ` [PATCH v3 22/40] cxl/core/hdm: Add CXL standard decoder enumeration to " Dan Williams
2022-01-26  3:09   ` [PATCH v4 " Dan Williams
2022-01-31 14:26     ` Jonathan Cameron
2022-01-31 17:51     ` Jonathan Cameron
2022-02-01  5:10       ` Dan Williams
2022-02-01 20:24     ` [PATCH v5 " Dan Williams
2022-02-02  9:31       ` Jonathan Cameron
2022-02-01  0:24   ` [PATCH v3 " Ben Widawsky
2022-02-01  4:58     ` Dan Williams
2022-01-24  0:30 ` [PATCH v3 23/40] cxl/core: Emit modalias for CXL devices Dan Williams
2022-01-31 17:57   ` Jonathan Cameron
2022-02-01 15:11   ` Ben Widawsky
2022-01-24  0:30 ` [PATCH v3 24/40] cxl/port: Add a driver for 'struct cxl_port' objects Dan Williams
2022-01-26 20:16   ` [PATCH v4 " Dan Williams
2022-01-31 18:11     ` Jonathan Cameron
2022-02-01 20:43       ` Dan Williams
2022-02-02  9:33         ` Jonathan Cameron
2022-02-01 21:07     ` [PATCH v5 " Dan Williams
2022-01-24  0:30 ` [PATCH v3 25/40] cxl/core/port: Remove @host argument for dport + decoder enumeration Dan Williams
2022-01-31 14:32   ` Jonathan Cameron
2022-01-31 18:14   ` Jonathan Cameron
2022-02-01 15:17   ` Ben Widawsky
2022-02-01 21:09     ` Dan Williams
2022-02-01 21:23   ` [PATCH v4 " Dan Williams
2022-01-24  0:30 ` [PATCH v3 26/40] cxl/pci: Store component register base in cxlds Dan Williams
2022-01-31 18:15   ` Jonathan Cameron
2022-02-01 21:28   ` [PATCH v4 " Dan Williams
2022-01-24  0:31 ` [PATCH v3 27/40] cxl/pci: Cache device DVSEC offset Dan Williams
2022-01-31 18:19   ` Jonathan Cameron
2022-02-01 15:24     ` Ben Widawsky
2022-02-01 21:41       ` Dan Williams
2022-02-01 22:11         ` Ben Widawsky
2022-02-01 22:15           ` Dan Williams
2022-02-01 22:20             ` Ben Widawsky
2022-02-01 22:24               ` Dan Williams
2022-02-02  9:36                 ` Jonathan Cameron
2022-02-01 22:06   ` [PATCH v4 " Dan Williams
2022-02-02  9:36     ` Jonathan Cameron
2022-01-24  0:31 ` [PATCH v3 28/40] cxl/pci: Retrieve CXL DVSEC memory info Dan Williams
2022-01-31 18:25   ` Jonathan Cameron
2022-02-01 22:52     ` Dan Williams
2022-02-01 23:48   ` [PATCH v4 " Dan Williams
2022-02-02  9:39     ` Jonathan Cameron
2022-01-24  0:31 ` [PATCH v3 29/40] cxl/pci: Implement wait for media active Dan Williams
2022-01-31 18:29   ` Jonathan Cameron
2022-02-01 23:56     ` Dan Williams
2022-01-24  0:31 ` [PATCH v3 30/40] cxl/pci: Emit device serial number Dan Williams
2022-01-31 18:33   ` Jonathan Cameron
2022-01-31 21:43     ` Dan Williams
2022-01-31 21:56   ` [PATCH v4 " Dan Williams
2022-01-24  0:31 ` [PATCH v3 31/40] cxl/memdev: Add numa_node attribute Dan Williams
2022-01-31 18:41   ` Jonathan Cameron
2022-02-01 23:57     ` Dan Williams
2022-02-02  9:44       ` Jonathan Cameron
2022-02-02 15:44         ` Dan Williams
2022-02-03  9:41           ` Jonathan Cameron
2022-02-03 16:59             ` Dan Williams
2022-02-03 18:05               ` Jonathan Cameron
2022-02-04  4:25                 ` Dan Williams
2022-02-01 15:31   ` Ben Widawsky
2022-02-01 15:49     ` Jonathan Cameron
2022-02-01 16:35       ` Ben Widawsky
2022-02-01 17:38         ` Jonathan Cameron
2022-02-01 23:59     ` Dan Williams
2022-02-02  1:18     ` Dan Williams
2022-01-24  0:31 ` [PATCH v3 32/40] cxl/core/port: Add switch port enumeration Dan Williams
2022-02-01 12:13   ` Jonathan Cameron
2022-02-02  5:26     ` Dan Williams
2022-02-01 17:37   ` Ben Widawsky
2022-02-02  6:03     ` Dan Williams
2022-02-02 17:07   ` [PATCH v4 " Dan Williams
2022-02-03  9:55     ` Jonathan Cameron
2022-02-04 15:08     ` [PATCH v5 " Dan Williams
2022-01-24  0:31 ` [PATCH v3 33/40] cxl/mem: Add the cxl_mem driver Dan Williams
2022-01-26  3:16   ` [PATCH v4 " Dan Williams
2022-02-01 12:45     ` Jonathan Cameron
2022-02-01 17:44       ` Ben Widawsky
2022-02-03  2:49       ` Dan Williams
2022-02-03  9:59         ` Jonathan Cameron
2022-02-04 14:54           ` Dan Williams
2022-02-03  3:56     ` [PATCH v5 " Dan Williams
2022-02-03 12:07       ` Jonathan Cameron
2022-02-04 15:18       ` [PATCH v6 " Dan Williams
2022-01-24  0:31 ` [PATCH v3 34/40] cxl/core: Move target_list out of base decoder attributes Dan Williams
2022-01-31 18:45   ` Jonathan Cameron
2022-02-01 17:45   ` Ben Widawsky
2022-01-24  0:31 ` [PATCH v3 35/40] cxl/core/port: Add endpoint decoders Dan Williams
2022-02-01 12:47   ` Jonathan Cameron
2022-02-03  4:02   ` [PATCH v4 " Dan Williams
2022-02-14 17:45     ` Jonathan Cameron
2022-02-14 19:14       ` Dan Williams
2022-01-24  0:31 ` [PATCH v3 36/40] tools/testing/cxl: Mock dvsec_ranges() Dan Williams
2022-01-24  0:31 ` [PATCH v3 37/40] tools/testing/cxl: Fix root port to host bridge assignment Dan Williams
2022-01-24  0:32 ` [PATCH v3 38/40] tools/testing/cxl: Mock one level of switches Dan Williams
2022-01-24  0:32 ` [PATCH v3 39/40] tools/testing/cxl: Enumerate mock decoders Dan Williams
2022-01-24  0:32 ` [PATCH v3 40/40] tools/testing/cxl: Add a physical_node link Dan Williams
2022-02-01 12:53   ` Jonathan Cameron

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