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From: "Marek Behún" <kabel@kernel.org>
To: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
	Bjorn Helgaas <helgaas@kernel.org>
Cc: "Krzysztof Wilczyński" <kw@linux.com>,
	"Marc Zyngier" <maz@kernel.org>,
	pali@kernel.org, linux-pci@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	"Gregory CLEMENT" <gregory.clement@bootlin.com>,
	"Marek Behún" <kabel@kernel.org>
Subject: [PATCH 17/18] PCI: aardvark: Run link training in separate worker
Date: Sun, 20 Feb 2022 20:33:45 +0100	[thread overview]
Message-ID: <20220220193346.23789-18-kabel@kernel.org> (raw)
In-Reply-To: <20220220193346.23789-1-kabel@kernel.org>

From: Pali Rohár <pali@kernel.org>

Link training and PCIe card reset routines in Aardvark contain several
delays, resulting in rather slow PCIe card probing. The worst case is
when there is no card connected: the driver tries link training at all
possible speeds and waits until all timers expire.

Since probe methods for all system devices are called sequentially, this
results in noticeably longer boot time.

Move card reset and link training code from driver probe function into
a separate worker, so that kernel can do something different while the
driver is waiting during reset or training.

On ESPRESSObin and Turris MOX this decreases boot time by 0.4s with
plugged PCIe card and by 2.2s if no card is connected.

Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Marek Behún <kabel@kernel.org>
---
 drivers/pci/controller/pci-aardvark.c | 42 ++++++++++++++++++---------
 1 file changed, 28 insertions(+), 14 deletions(-)

diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c
index 8c9ac7766ac7..056f49d0e3a4 100644
--- a/drivers/pci/controller/pci-aardvark.c
+++ b/drivers/pci/controller/pci-aardvark.c
@@ -26,6 +26,7 @@
 #include <linux/of_gpio.h>
 #include <linux/of_pci.h>
 #include <linux/timer.h>
+#include <linux/workqueue.h>
 
 #include "../pci.h"
 #include "../pci-bridge-emul.h"
@@ -296,6 +297,8 @@ struct advk_pcie {
 	int link_gen;
 	bool link_was_up;
 	struct timer_list link_irq_timer;
+	struct delayed_work probe_card_work;
+	bool host_bridge_probed;
 	struct pci_bridge_emul bridge;
 	struct gpio_desc *reset_gpio;
 	struct clk *clk;
@@ -497,6 +500,21 @@ static void advk_pcie_train_link(struct advk_pcie *pcie)
 		dev_err(dev, "link never came up\n");
 }
 
+static void advk_pcie_probe_card_work(struct work_struct *work)
+{
+	struct delayed_work *dwork = container_of(work, struct delayed_work,
+						  work);
+	struct advk_pcie *pcie = container_of(dwork, struct advk_pcie,
+					      probe_card_work);
+	struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie);
+	int ret;
+
+	advk_pcie_train_link(pcie);
+	ret = pci_host_probe(bridge);
+	if (!ret)
+		pcie->host_bridge_probed = true;
+}
+
 /*
  * Set PCIe address window register which could be used for memory
  * mapping.
@@ -701,8 +719,6 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie)
 	/* Disable remaining PCIe outbound windows */
 	for (i = pcie->wins_count; i < OB_WIN_COUNT; i++)
 		advk_pcie_disable_ob_win(pcie, i);
-
-	advk_pcie_train_link(pcie);
 }
 
 static int advk_pcie_check_pio_status(struct advk_pcie *pcie, bool allow_crs, u32 *val)
@@ -2112,14 +2128,8 @@ static int advk_pcie_probe(struct platform_device *pdev)
 	bridge->ops = &advk_pcie_ops;
 	bridge->map_irq = advk_pcie_map_irq;
 
-	ret = pci_host_probe(bridge);
-	if (ret < 0) {
-		irq_set_chained_handler_and_data(pcie->irq, NULL, NULL);
-		advk_pcie_remove_rp_irq_domain(pcie);
-		advk_pcie_remove_msi_irq_domain(pcie);
-		advk_pcie_remove_irq_domain(pcie);
-		return ret;
-	}
+	INIT_DELAYED_WORK(&pcie->probe_card_work, advk_pcie_probe_card_work);
+	schedule_delayed_work(&pcie->probe_card_work, 1);
 
 	return 0;
 }
@@ -2131,11 +2141,15 @@ static int advk_pcie_remove(struct platform_device *pdev)
 	u32 val;
 	int i;
 
+	cancel_delayed_work_sync(&pcie->probe_card_work);
+
 	/* Remove PCI bus with all devices */
-	pci_lock_rescan_remove();
-	pci_stop_root_bus(bridge->bus);
-	pci_remove_root_bus(bridge->bus);
-	pci_unlock_rescan_remove();
+	if (pcie->host_bridge_probed) {
+		pci_lock_rescan_remove();
+		pci_stop_root_bus(bridge->bus);
+		pci_remove_root_bus(bridge->bus);
+		pci_unlock_rescan_remove();
+	}
 
 	/* Disable Root Bridge I/O space, memory space and bus mastering */
 	val = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG);
-- 
2.34.1


  parent reply	other threads:[~2022-02-20 19:34 UTC|newest]

Thread overview: 44+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-02-20 19:33 [PATCH 00/18] PCI: aardvark controller changes BATCH 5 Marek Behún
2022-02-20 19:33 ` [PATCH 01/18] PCI: pci-bridge-emul: Re-arrange register tests Marek Behún
2022-02-20 19:33 ` [PATCH 02/18] PCI: pci-bridge-emul: Add support for PCIe extended capabilities Marek Behún
2022-02-20 19:33 ` [PATCH 03/18] PCI: aardvark: Add support for AER registers on emulated bridge Marek Behún
2022-02-20 19:33 ` [PATCH 04/18] PCI: Add PCI_EXP_SLTCAP_*_SHIFT macros Marek Behún
2022-04-28 11:09   ` Lorenzo Pieralisi
2022-04-28 11:16     ` Pali Rohár
2022-05-18 19:23   ` Bjorn Helgaas
2022-05-18 19:26     ` Pali Rohár
2022-05-18 20:05       ` Marek Behún
2022-05-18 20:27         ` Bjorn Helgaas
2022-02-20 19:33 ` [PATCH 05/18] PCI: aardvark: Fix reporting Slot capabilities on emulated bridge Marek Behún
2022-02-20 19:33 ` [PATCH 06/18] PCI: pciehp: Enable DLLSC interrupt only if supported Marek Behún
2022-05-09  3:42   ` Lukas Wunner
2022-05-13 16:57     ` Pali Rohár
2022-05-14  9:14       ` Lukas Wunner
2022-08-18 12:22         ` Marek Behún
2022-02-20 19:33 ` [PATCH 07/18] PCI: pciehp: Enable Command Completed Interrupt " Marek Behún
2022-05-09  4:01   ` Lukas Wunner
2022-05-13 16:59     ` Pali Rohár
2022-02-20 19:33 ` [PATCH 08/18] PCI: aardvark: Add support for DLLSC and hotplug interrupt Marek Behún
2022-02-20 19:33 ` [PATCH 09/18] PCI: Add PCI_EXP_SLTCTL_ASPL_DISABLE macro Marek Behún
2022-02-20 19:33 ` [PATCH 10/18] PCI: Add function for parsing `slot-power-limit-milliwatt` DT property Marek Behún
2022-02-20 19:33 ` [PATCH 11/18] dt-bindings: PCI: aardvark: Describe slot-power-limit-milliwatt Marek Behún
2022-02-20 19:33 ` [PATCH 12/18] PCI: aardvark: Send Set_Slot_Power_Limit message Marek Behún
2022-02-20 19:33 ` [PATCH 13/18] arm64: dts: armada-3720-turris-mox: Define slot-power-limit-milliwatt for PCIe Marek Behún
2022-02-20 19:33 ` [PATCH 14/18] PCI: aardvark: Add clock support Marek Behún
2022-02-20 19:33 ` [PATCH 15/18] arm64: dts: marvell: armada-37xx: Add clock to PCIe node Marek Behún
2022-02-28 15:52   ` Gregory CLEMENT
2022-02-20 19:33 ` [PATCH 16/18] PCI: aardvark: Add suspend to RAM support Marek Behún
2022-04-12 11:14   ` Lorenzo Pieralisi
2022-02-20 19:33 ` Marek Behún [this message]
2022-04-12 15:25   ` [PATCH 17/18] PCI: aardvark: Run link training in separate worker Lorenzo Pieralisi
2022-04-12 17:55     ` Pali Rohár
2022-04-13  9:16       ` Lorenzo Pieralisi
2022-05-04 14:02         ` Marek Behún
2022-02-20 19:33 ` [PATCH 18/18] PCI: aardvark: Optimize PCIe card reset via GPIO Marek Behún
2022-04-11 15:36 ` [PATCH 00/18] PCI: aardvark controller changes BATCH 5 Lorenzo Pieralisi
2022-04-11 16:53   ` Pali Rohár
2022-05-13 10:33 ` Lorenzo Pieralisi
2022-05-13 16:48   ` Pali Rohár
2022-05-18 15:54 ` (subset) " Lorenzo Pieralisi
2022-08-16 16:25 ` Lorenzo Pieralisi
2022-08-18 13:56   ` Marek Behún

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