[PATCH v4 1/2] ARM: dts: imx6qp-sabresd: Enable PCIe support

[PATCH v4 1/2] ARM: dts: imx6qp-sabresd: Enable PCIe support

[Richard Zhu]

In the i.MX6QP sabresd board(sch-28857) design, one external oscillator
is powered up by vgen3 and used as the PCIe reference clock source by
the endpoint device.

If RC uses this oscillator as reference clock too, PLL6(ENET PLL) would
has to be in bypass mode, and ENET clocks would be messed up.

To keep things simple, let RC use the internal PLL as reference clock
and set vgen3 always on to enable the external oscillator for endpoint
device on i.MX6QP sabresd board.

NOTE: This reference clock setup is used to pass the GEN2 TX compliance
tests, and isn't recommended as a setup in the end-user design.

Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
---
 arch/arm/boot/dts/imx6qp-sabresd.dts | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/imx6qp-sabresd.dts b/arch/arm/boot/dts/imx6qp-sabresd.dts
index 480e73183f6b..f69eec18d865 100644
--- a/arch/arm/boot/dts/imx6qp-sabresd.dts
+++ b/arch/arm/boot/dts/imx6qp-sabresd.dts
@@ -50,8 +50,12 @@ MX6QDL_PAD_SD3_DAT7__SD3_DATA7		0x17059
 	};
 };
 
+&vgen3_reg {
+	regulator-always-on;
+};
+
 &pcie {
-	status = "disabled";
+	status = "okay";
 };
 
 &sata {
-- 
2.25.1

[PATCH v4 2/2] PCI: imx6: Enable i.MX6QP PCIe power management support

[Richard Zhu]

i.MX6QP PCIe supports the reset logic, thus it can reset itself to the
initialized state when exit from L2 or L3 states.

Enable the i.MX6QP PCIe suspend/resume operations support.

Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
---
 drivers/pci/controller/dwc/pci-imx6.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
index 784801f2f9e6..62262483470a 100644
--- a/drivers/pci/controller/dwc/pci-imx6.c
+++ b/drivers/pci/controller/dwc/pci-imx6.c
@@ -995,6 +995,7 @@ static void imx6_pcie_pm_turnoff(struct imx6_pcie *imx6_pcie)
 	/* Others poke directly at IOMUXC registers */
 	switch (imx6_pcie->drvdata->variant) {
 	case IMX6SX:
+	case IMX6QP:
 		regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
 				IMX6SX_GPR12_PCIE_PM_TURN_OFF,
 				IMX6SX_GPR12_PCIE_PM_TURN_OFF);
@@ -1307,7 +1308,8 @@ static const struct imx6_pcie_drvdata drvdata[] = {
 	[IMX6QP] = {
 		.variant = IMX6QP,
 		.flags = IMX6_PCIE_FLAG_IMX6_PHY |
-			 IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE,
+			 IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE |
+			 IMX6_PCIE_FLAG_SUPPORTS_SUSPEND,
 		.dbi_length = 0x200,
 	},
 	[IMX7D] = {
-- 
2.25.1

Re: [PATCH v4 1/2] ARM: dts: imx6qp-sabresd: Enable PCIe support

[Shawn Guo]

On Mon, Feb 21, 2022 at 02:33:56PM +0800, Richard Zhu wrote:
> In the i.MX6QP sabresd board(sch-28857) design, one external oscillator
> is powered up by vgen3 and used as the PCIe reference clock source by
> the endpoint device.
> 
> If RC uses this oscillator as reference clock too, PLL6(ENET PLL) would
> has to be in bypass mode, and ENET clocks would be messed up.
> 
> To keep things simple, let RC use the internal PLL as reference clock
> and set vgen3 always on to enable the external oscillator for endpoint
> device on i.MX6QP sabresd board.
> 
> NOTE: This reference clock setup is used to pass the GEN2 TX compliance
> tests, and isn't recommended as a setup in the end-user design.
> 
> Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>

Applied, thanks!

Re: (subset) [PATCH v4 1/2] ARM: dts: imx6qp-sabresd: Enable PCIe support

[Lorenzo Pieralisi]

On Mon, 21 Feb 2022 14:33:56 +0800, Richard Zhu wrote:
> In the i.MX6QP sabresd board(sch-28857) design, one external oscillator
> is powered up by vgen3 and used as the PCIe reference clock source by
> the endpoint device.
> 
> If RC uses this oscillator as reference clock too, PLL6(ENET PLL) would
> has to be in bypass mode, and ENET clocks would be messed up.
> 
> [...]

I skipped patch(1) since we don't apply dts changes, those should
go via respective platform maintainers.

[2/2] PCI: imx6: Enable i.MX6QP PCIe power management support
      https://git.kernel.org/lpieralisi/pci/c/f81dd043ec

Thanks,
Lorenzo

RE: (subset) [PATCH v4 1/2] ARM: dts: imx6qp-sabresd: Enable PCIe support

[Hongxing Zhu]

> -----Original Message-----
> From: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
> Sent: 2022年3月7日 19:10
> To: shawnguo@kernel.org; Hongxing Zhu <hongxing.zhu@nxp.com>;
> bhelgaas@google.com; l.stach@pengutronix.de
> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>; kernel@pengutronix.de;
> linux-arm-kernel@lists.infradead.org; linux-kernel@vger.kernel.org;
> dl-linux-imx <linux-imx@nxp.com>; linux-pci@vger.kernel.org
> Subject: Re: (subset) [PATCH v4 1/2] ARM: dts: imx6qp-sabresd: Enable PCIe
> support
> 
> On Mon, 21 Feb 2022 14:33:56 +0800, Richard Zhu wrote:
> > In the i.MX6QP sabresd board(sch-28857) design, one external
> > oscillator is powered up by vgen3 and used as the PCIe reference clock
> > source by the endpoint device.
> >
> > If RC uses this oscillator as reference clock too, PLL6(ENET PLL)
> > would has to be in bypass mode, and ENET clocks would be messed up.
> >
> > [...]
> 
> I skipped patch(1) since we don't apply dts changes, those should go via
> respective platform maintainers.
Understand, thanks for your help.

Best Regards
Richard Zhu
> 
> [2/2] PCI: imx6: Enable i.MX6QP PCIe power management support
> 
> https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgit.kern
> el.org%2Flpieralisi%2Fpci%2Fc%2Ff81dd043ec&amp;data=04%7C01%7Chong
> xing.zhu%40nxp.com%7Cc6ab1b9cf18744b9516108da002b06f3%7C686ea1d
> 3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C637822482058252728%7CUnkn
> own%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1
> haWwiLCJXVCI6Mn0%3D%7C3000&amp;sdata=9pUAm3FYUtbKabnhiD7aV0v
> mPrBCwa%2F7u2GBQLaxBZ0%3D&amp;reserved=0
> 
> Thanks,
> Lorenzo