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[75.80.179.40]) by smtp.gmail.com with ESMTPSA id z12-20020aa7888c000000b004f3fc6d95casm25503039pfe.20.2022.03.15.12.52.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Mar 2022 12:52:58 -0700 (PDT) Date: Tue, 15 Mar 2022 12:52:55 -0700 From: Eric Badger To: Sathyanarayanan Kuppuswamy Cc: Bjorn Helgaas , Russell Currey , Oliver OHalloran , linux-pci@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org, ebadger@purestorage.com Subject: Re: [PATCH v2] PCI/AER: Handle Multi UnCorrectable/Correctable errors properly Message-ID: <20220315195255.GA1523195@ebps> References: <20220315050842.120063-1-sathyanarayanan.kuppuswamy@linux.intel.com> <20220315171425.GA1521135@ebps> <2d4e8811-dce6-c891-e92d-e3746434685e@linux.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <2d4e8811-dce6-c891-e92d-e3746434685e@linux.intel.com> Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org On Tue, Mar 15, 2022 at 10:26:46AM -0700, Sathyanarayanan Kuppuswamy wrote: > On 3/15/22 10:14 AM, Eric Badger wrote: > > > # Prep injection data for a correctable error. > > > $ cd /sys/kernel/debug/apei/einj > > > $ echo 0x00000040 > error_type > > > $ echo 0x4 > flags > > > $ echo 0x891000 > param4 > > > > > > # Root Error Status is initially clear > > > $ setpci -s ECAP0001+0x30.w > > > 0000 > > > > > > # Inject one error > > > $ echo 1 > error_inject > > > > > > # Interrupt received > > > pcieport : AER: Root Error Status 0001 > > > > > > # Inject another error (within 5 seconds) > > > $ echo 1 > error_inject > > > > > > # No interrupt received, but "multiple ERR_COR" is now set > > > $ setpci -s ECAP0001+0x30.w > > > 0003 > > > > > > # Wait for a while, then clear ERR_COR. A new interrupt immediately > > > fires. > > > $ setpci -s ECAP0001+0x30.w=0x1 > > > pcieport : AER: Root Error Status 0002 > > > > > > Currently, the above issue has been only reproduced in the ICL server > > > platform. > > > > > > [Eric: proposed reproducing steps] > > Hmm, this differs from the procedure I described on v1, and I don't > > think will work as described here. > > I have attempted to modify the steps to reproduce it without returning > IRQ_NONE for all cases (which will break the functionality). But I > think I did not correct the last few steps. Well, the thinking in always returning IRQ_NONE was so that only setpci modified the register and we could clearly see how writes to the register affect interrupt generation. > How about replacing the last 3 steps with following? > > # Inject another error (within 5 seconds) > $ echo 1 > error_inject > > # You will get a new IRQ with only multiple ERR_COR bit set > pcieport : AER: Root Error Status 0002 This seems accurate. Though it does muddy a detail that I think was clearer in the original procedure: was the second interrupt triggered by the second error, or by the write of 0x1 to Root Error Status? Also, in terms of practically running the test, I find the mdelay() can block other interrupts and can make running the test sort of confusing ("is it not printing because the interrupt didn't fire, or because it's spinning and blocking my NIC driver?" :). Cheers, Eric