Re: [PATCH 7/8] cxl/pci: Find and map the RAS Capability Structure

[Jonathan Cameron <Jonathan.Cameron@Huawei.com>]

On Tue, 15 Mar 2022 21:14:19 -0700
Dan Williams <dan.j.williams@intel.com> wrote:

> The RAS Capability Structure has some ancillary information that may be
> relevant with respect to AER events, link and protcol error status
> registers. Map the RAS Capability Registers in support of defining a
> 'struct pci_error_handlers' instance for the cxl_pci driver.
> 
> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Looks right to me.

Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>

> ---
>  drivers/cxl/core/regs.c |    7 +++++++
>  drivers/cxl/cxl.h       |   19 +++++++++++++++++++
>  drivers/cxl/pci.c       |    8 ++++++++
>  3 files changed, 34 insertions(+)
> 
> diff --git a/drivers/cxl/core/regs.c b/drivers/cxl/core/regs.c
> index c022c8937dfc..53aac68b9ce4 100644
> --- a/drivers/cxl/core/regs.c
> +++ b/drivers/cxl/core/regs.c
> @@ -83,6 +83,12 @@ void cxl_probe_component_regs(struct device *dev, void __iomem *base,
>  			rmap = &map->hdm_decoder;
>  			break;
>  		}
> +		case CXL_CM_CAP_CAP_ID_RAS:
> +			dev_dbg(dev, "found RAS capability (0x%x)\n",
> +				offset);
> +			length = CXL_RAS_CAPABILITY_LENGTH;
> +			rmap = &map->ras;
> +			break;
>  		default:
>  			dev_dbg(dev, "Unknown CM cap ID: %d (0x%x)\n", cap_id,
>  				offset);
> @@ -196,6 +202,7 @@ int cxl_map_component_regs(struct device *dev, struct cxl_component_regs *regs,
>  		void __iomem **addr;
>  	} mapinfo[] = {
>  		{ .rmap = &map->component_map.hdm_decoder, &regs->hdm_decoder },
> +		{ .rmap = &map->component_map.ras, &regs->ras },
>  	};
>  	int i;
>  
> diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
> index 52bd77d8e22a..cf3d8d0aaf22 100644
> --- a/drivers/cxl/cxl.h
> +++ b/drivers/cxl/cxl.h
> @@ -32,6 +32,7 @@
>  #define   CXL_CM_CAP_HDR_ARRAY_SIZE_MASK GENMASK(31, 24)
>  #define CXL_CM_CAP_PTR_MASK GENMASK(31, 20)
>  
> +#define   CXL_CM_CAP_CAP_ID_RAS 0x2
>  #define   CXL_CM_CAP_CAP_ID_HDM 0x5
>  #define   CXL_CM_CAP_CAP_HDM_VERSION 1
>  
> @@ -64,6 +65,21 @@ static inline int cxl_hdm_decoder_count(u32 cap_hdr)
>  	return val ? val * 2 : 1;
>  }
>  
> +/* RAS Registers CXL 2.0 8.2.5.9 CXL RAS Capability Structure */
> +#define CXL_RAS_UNCORRECTABLE_STATUS_OFFSET 0x0
> +#define   CXL_RAS_UNCORRECTABLE_STATUS_MASK (GENMASK(16, 14) | GENMASK(11, 0))
> +#define CXL_RAS_UNCORRECTABLE_MASK_OFFSET 0x4
> +#define   CXL_RAS_UNCORRECTABLE_MASK_MASK (GENMASK(16, 14) | GENMASK(11, 0))
> +#define CXL_RAS_UNCORRECTABLE_SEVERITY_OFFSET 0x8
> +#define   CXL_RAS_UNCORRECTABLE_SEVERITY_MASK (GENMASK(16, 14) | GENMASK(11, 0))
> +#define CXL_RAS_CORRECTABLE_STATUS_OFFSET 0xC
> +#define   CXL_RAS_CORRECTABLE_STATUS_MASK GENMASK(6, 0)
> +#define CXL_RAS_CORRECTABLE_MASK_OFFSET 0x10
> +#define   CXL_RAS_CORRECTABLE_MASK_MASK GENMASK(6, 0)
> +#define CXL_RAS_CAP_CONTROL_OFFSET 0x14
> +#define CXL_RAS_HEADER_LOG_OFFSET 0x18
> +#define CXL_RAS_CAPABILITY_LENGTH 0x58
> +
>  /* CXL 2.0 8.2.8.1 Device Capabilities Array Register */
>  #define CXLDEV_CAP_ARRAY_OFFSET 0x0
>  #define   CXLDEV_CAP_ARRAY_CAP_ID 0
> @@ -98,9 +114,11 @@ struct cxl_regs {
>  	/*
>  	 * Common set of CXL Component register block base pointers
>  	 * @hdm_decoder: CXL 2.0 8.2.5.12 CXL HDM Decoder Capability Structure
> +	 * @ras: CXL 2.0 8.2.5.9 CXL RAS Capability Structure
>  	 */
>  	struct_group_tagged(cxl_component_regs, component,
>  		void __iomem *hdm_decoder;
> +		void __iomem *ras;
>  	);
>  	/*
>  	 * Common set of CXL Device register block base pointers
> @@ -122,6 +140,7 @@ struct cxl_reg_map {
>  
>  struct cxl_component_reg_map {
>  	struct cxl_reg_map hdm_decoder;
> +	struct cxl_reg_map ras;
>  };
>  
>  struct cxl_device_reg_map {
> diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c
> index d8361331a013..bde8929450f0 100644
> --- a/drivers/cxl/pci.c
> +++ b/drivers/cxl/pci.c
> @@ -310,6 +310,9 @@ static int cxl_probe_regs(struct pci_dev *pdev, struct cxl_register_map *map)
>  			return -ENXIO;
>  		}
>  
> +		if (!comp_map->ras.valid)
> +			dev_dbg(dev, "RAS registers not found\n");
> +
>  		dev_dbg(dev, "Set up component registers\n");
>  		break;
>  	case CXL_REGLOC_RBI_MEMDEV:
> @@ -580,6 +583,11 @@ static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
>  
>  	cxlds->component_reg_phys = map.resource;
>  
> +	rc = cxl_map_component_regs(&pdev->dev, &cxlds->regs.component,
> +				    &map, BIT(CXL_CM_CAP_CAP_ID_RAS));
> +	if (rc)
> +		dev_dbg(&pdev->dev, "Failed to map RAS capability.\n");
> +
>  	rc = cxl_pci_setup_mailbox(cxlds);
>  	if (rc)
>  		return rc;
>