From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
To: "Andy Gross" <agross@kernel.org>,
"Bjorn Andersson" <bjorn.andersson@linaro.org>,
"Stephen Boyd" <swboyd@chromium.org>,
"Michael Turquette" <mturquette@baylibre.com>,
"Taniya Das" <tdas@codeaurora.org>,
"Lorenzo Pieralisi" <lorenzo.pieralisi@arm.com>,
"Krzysztof Wilczyński" <kw@linux.com>,
"Bjorn Helgaas" <bhelgaas@google.com>
Cc: Prasad Malisetty <quic_pmaliset@quicinc.com>,
linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org,
linux-pci@vger.kernel.org
Subject: [PATCH v3 4/6] clk: qcom: gcc-sc7280: use new clk_regmap_mux_safe_ops for PCIe pipe clocks
Date: Thu, 14 Apr 2022 02:31:42 +0300 [thread overview]
Message-ID: <20220413233144.275926-5-dmitry.baryshkov@linaro.org> (raw)
In-Reply-To: <20220413233144.275926-1-dmitry.baryshkov@linaro.org>
Use newly defined clk_regmap_mux_safe_ops for PCIe pipe clocks to let
the clock framework automatically park the clock when the clock is
switched off and restore the parent when the clock is switched on.
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/clk/qcom/gcc-sc7280.c | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/qcom/gcc-sc7280.c b/drivers/clk/qcom/gcc-sc7280.c
index 423627d49719..e1ce3e635236 100644
--- a/drivers/clk/qcom/gcc-sc7280.c
+++ b/drivers/clk/qcom/gcc-sc7280.c
@@ -373,13 +373,15 @@ static struct clk_regmap_mux gcc_pcie_0_pipe_clk_src = {
.reg = 0x6b054,
.shift = 0,
.width = 2,
+ .safe_src_parent = P_BI_TCXO,
+ .stored_parent = P_PCIE_0_PIPE_CLK,
.parent_map = gcc_parent_map_6,
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_pipe_clk_src",
.parent_data = gcc_parent_data_6,
.num_parents = ARRAY_SIZE(gcc_parent_data_6),
- .ops = &clk_regmap_mux_closest_ops,
+ .ops = &clk_regmap_mux_safe_ops,
},
},
};
@@ -388,13 +390,15 @@ static struct clk_regmap_mux gcc_pcie_1_pipe_clk_src = {
.reg = 0x8d054,
.shift = 0,
.width = 2,
+ .safe_src_parent = P_BI_TCXO,
+ .stored_parent = P_PCIE_1_PIPE_CLK,
.parent_map = gcc_parent_map_7,
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_1_pipe_clk_src",
.parent_data = gcc_parent_data_7,
.num_parents = ARRAY_SIZE(gcc_parent_data_7),
- .ops = &clk_regmap_mux_closest_ops,
+ .ops = &clk_regmap_mux_safe_ops,
},
},
};
--
2.35.1
next prev parent reply other threads:[~2022-04-13 23:31 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-04-13 23:31 [PATCH v3 0/6] PCI: qcom: rework pipe_clk/pipe_clk_src handling Dmitry Baryshkov
2022-04-13 23:31 ` [PATCH v3 1/6] clk: qcom: add two parent_map helpers Dmitry Baryshkov
2022-04-13 23:31 ` [PATCH v3 2/6] clk: qcom: regmap-mux: add pipe clk implementation Dmitry Baryshkov
2022-04-13 23:31 ` [PATCH v3 3/6] clk: qcom: gcc-sm8450: use new clk_regmap_mux_safe_ops for PCIe pipe clocks Dmitry Baryshkov
2022-04-13 23:31 ` Dmitry Baryshkov [this message]
2022-04-13 23:31 ` [PATCH v3 5/6] PCI: qcom: Remove unnecessary pipe_clk handling Dmitry Baryshkov
2022-04-13 23:31 ` [PATCH v3 6/6] PCI: qcom: Drop manual pipe_clk_src handling Dmitry Baryshkov
2022-04-21 10:28 ` [PATCH v3 0/6] PCI: qcom: rework pipe_clk/pipe_clk_src handling Johan Hovold
2022-04-21 11:37 ` Dmitry Baryshkov
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