From: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
To: Frank Li <Frank.Li@nxp.com>
Cc: gustavo.pimentel@synopsys.com, hongxing.zhu@nxp.com,
l.stach@pengutronix.de, linux-imx@nxp.com,
linux-pci@vger.kernel.org, dmaengine@vger.kernel.org,
fancer.lancer@gmail.com, lznuaa@gmail.com, helgaas@kernel.org,
vkoul@kernel.org, lorenzo.pieralisi@arm.com, robh@kernel.org,
kw@linux.com, bhelgaas@google.com,
Sergey.Semin@baikalelectronics.ru
Subject: Re: [PATCH v9 3/9] dmaengine: dw-edma: Change rg_region to reg_base in struct dw_edma_chip
Date: Sat, 23 Apr 2022 17:29:02 +0530 [thread overview]
Message-ID: <20220423115902.GF374560@thinkpad> (raw)
In-Reply-To: <20220422143643.727871-4-Frank.Li@nxp.com>
On Fri, Apr 22, 2022 at 09:36:37AM -0500, Frank Li wrote:
> struct dw_edma_region rg_region included virtual address, physical
> address and size informaiton. But only virtual address is used by EDMA
information
> driver. Change it to void __iomem *reg_base to clean up code.
>
> Signed-off-by: Frank Li <Frank.Li@nxp.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Thanks,
Mani
> Reviewed-by: Serge Semin <fancer.lancer@gmail.com>
> ---
> Change from v6 to v9:
> - none
> Change from v5 to v6:
> -s/change/Change at subject
> New patch at v4
>
>
> drivers/dma/dw-edma/dw-edma-pcie.c | 6 +++---
> drivers/dma/dw-edma/dw-edma-v0-core.c | 2 +-
> drivers/dma/dw-edma/dw-edma-v0-debugfs.c | 2 +-
> include/linux/dma/edma.h | 3 ++-
> 4 files changed, 7 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/dma/dw-edma/dw-edma-pcie.c b/drivers/dma/dw-edma/dw-edma-pcie.c
> index 2c1c5fa4e9f28..ae42bad24dd5a 100644
> --- a/drivers/dma/dw-edma/dw-edma-pcie.c
> +++ b/drivers/dma/dw-edma/dw-edma-pcie.c
> @@ -233,8 +233,8 @@ static int dw_edma_pcie_probe(struct pci_dev *pdev,
> chip->wr_ch_cnt = vsec_data.wr_ch_cnt;
> chip->rd_ch_cnt = vsec_data.rd_ch_cnt;
>
> - chip->rg_region.vaddr = pcim_iomap_table(pdev)[vsec_data.rg.bar];
> - if (!chip->rg_region.vaddr)
> + chip->reg_base = pcim_iomap_table(pdev)[vsec_data.rg.bar];
> + if (!chip->reg_base)
> return -ENOMEM;
>
> for (i = 0; i < chip->wr_ch_cnt; i++) {
> @@ -299,7 +299,7 @@ static int dw_edma_pcie_probe(struct pci_dev *pdev,
>
> pci_dbg(pdev, "Registers:\tBAR=%u, off=0x%.8lx, sz=0x%zx bytes, addr(v=%p)\n",
> vsec_data.rg.bar, vsec_data.rg.off, vsec_data.rg.sz,
> - chip->rg_region.vaddr);
> + chip->reg_base);
>
>
> for (i = 0; i < chip->wr_ch_cnt; i++) {
> diff --git a/drivers/dma/dw-edma/dw-edma-v0-core.c b/drivers/dma/dw-edma/dw-edma-v0-core.c
> index 6cf6c28ce0cc9..c59e23b9f9fdb 100644
> --- a/drivers/dma/dw-edma/dw-edma-v0-core.c
> +++ b/drivers/dma/dw-edma/dw-edma-v0-core.c
> @@ -25,7 +25,7 @@ enum dw_edma_control {
>
> static inline struct dw_edma_v0_regs __iomem *__dw_regs(struct dw_edma *dw)
> {
> - return dw->chip->rg_region.vaddr;
> + return dw->chip->reg_base;
> }
>
> #define SET_32(dw, name, value) \
> diff --git a/drivers/dma/dw-edma/dw-edma-v0-debugfs.c b/drivers/dma/dw-edma/dw-edma-v0-debugfs.c
> index da88958399a95..f59e7c37feac3 100644
> --- a/drivers/dma/dw-edma/dw-edma-v0-debugfs.c
> +++ b/drivers/dma/dw-edma/dw-edma-v0-debugfs.c
> @@ -287,7 +287,7 @@ void dw_edma_v0_debugfs_on(struct dw_edma *dw)
> if (!dw)
> return;
>
> - regs = dw->chip->rg_region.vaddr;
> + regs = dw->chip->reg_base;
> if (!regs)
> return;
>
> diff --git a/include/linux/dma/edma.h b/include/linux/dma/edma.h
> index 6fd374cc72c8e..e9ce652b88233 100644
> --- a/include/linux/dma/edma.h
> +++ b/include/linux/dma/edma.h
> @@ -39,6 +39,7 @@ enum dw_edma_map_format {
> * @id: instance ID
> * @nr_irqs: total dma irq number
> * @ops DMA channel to IRQ number mapping
> + * @reg_base DMA register base address
> * @wr_ch_cnt DMA write channel number
> * @rd_ch_cnt DMA read channel number
> * @rg_region DMA register region
> @@ -53,7 +54,7 @@ struct dw_edma_chip {
> int nr_irqs;
> const struct dw_edma_core_ops *ops;
>
> - struct dw_edma_region rg_region;
> + void __iomem *reg_base;
>
> u16 wr_ch_cnt;
> u16 rd_ch_cnt;
> --
> 2.35.1
>
next prev parent reply other threads:[~2022-04-23 11:59 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-04-22 14:36 [PATCH v9 0/9] Enable designware PCI EP EDMA locally Frank Li
2022-04-22 14:36 ` [PATCH v9 1/9] dmaengine: dw-edma: Remove unused field irq in struct dw_edma_chip Frank Li
2022-04-23 11:49 ` Manivannan Sadhasivam
2022-04-22 14:36 ` [PATCH v9 2/9] dmaengine: dw-edma: Detach the private data and chip info structures Frank Li
2022-04-22 17:23 ` Serge Semin
2022-04-23 11:57 ` Manivannan Sadhasivam
2022-04-22 14:36 ` [PATCH v9 3/9] dmaengine: dw-edma: Change rg_region to reg_base in struct dw_edma_chip Frank Li
2022-04-23 11:59 ` Manivannan Sadhasivam [this message]
2022-04-22 14:36 ` [PATCH v9 4/9] dmaengine: dw-edma: Rename wr(rd)_ch_cnt to ll_wr(rd)_cnt " Frank Li
2022-04-23 12:12 ` Manivannan Sadhasivam
2022-04-23 21:47 ` Zhi Li
2022-04-27 16:45 ` Zhi Li
2022-04-27 17:18 ` Manivannan Sadhasivam
2022-04-22 14:36 ` [PATCH v9 5/9] dmaengine: dw-edma: Drop dma_slave_config.direction field usage Frank Li
2022-04-22 14:36 ` [PATCH v9 6/9] dmaengine: dw-edma: Fix eDMA Rd/Wr-channels and DMA-direction semantics Frank Li
2022-04-22 14:36 ` [PATCH v9 7/9] dmaengine: dw-edma: Add support for chip specific flags Frank Li
2022-04-23 12:14 ` Manivannan Sadhasivam
2022-04-22 14:36 ` [PATCH v9 8/9] dmaengine: dw-edma: Add DW_EDMA_CHIP_32BIT_DBI " Frank Li
2022-04-23 12:16 ` Manivannan Sadhasivam
2022-04-22 14:36 ` [PATCH v9 9/9] PCI: endpoint: Add embedded DMA controller test Frank Li
2022-04-23 12:20 ` Manivannan Sadhasivam
2022-04-27 9:30 ` Lorenzo Pieralisi
2022-04-27 17:01 ` Zhi Li
2022-04-29 15:38 ` Zhi Li
2022-04-22 17:53 ` [PATCH v9 0/9] Enable designware PCI EP EDMA locally Serge Semin
2022-04-22 17:57 ` Zhi Li
2022-04-22 18:13 ` Serge Semin
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