From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4835DC433FE for ; Wed, 27 Apr 2022 17:18:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232632AbiD0RVv (ORCPT ); Wed, 27 Apr 2022 13:21:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33990 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231210AbiD0RVu (ORCPT ); Wed, 27 Apr 2022 13:21:50 -0400 Received: from mail-pl1-x633.google.com (mail-pl1-x633.google.com [IPv6:2607:f8b0:4864:20::633]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B928E4349D for ; Wed, 27 Apr 2022 10:18:34 -0700 (PDT) Received: by mail-pl1-x633.google.com with SMTP id h12so2105627plf.12 for ; Wed, 27 Apr 2022 10:18:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to; bh=ZNzLVb6IYQOQv9U2eS6LqWegFjblxsHIEuJynYwzEGc=; b=aCqN21episAYOq2l82EB/yHcNnat6tZvY04o7oNbYHLafKqkBN61WjW970RUu7zqkn nNFUca/Nc1Kg8XpNSBtDYjHvVMBPrbBw3GM/WRJEZBXmqwvHxi9VvpCFI3q6Jgh71rhw vVXh1PH50/g65qGVAfHxdZFkGrcX75L/7RElLrLyZDCiKK4xkyzNMW/OgsAac+m57Ico pMGMuALK3wujfzkL/GftiCTr3aA845ytnKwrcrdBjKjBFvcR7+eunnmsOr3mnz7prpIu i/xoAOuiezzOcNtFnOi1wAjbOqPE2gDzFFcMNOeLs9Dd3+TtpQDLzb70hq7/B1judgYK qecg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=ZNzLVb6IYQOQv9U2eS6LqWegFjblxsHIEuJynYwzEGc=; b=VLXKBCH0TRXNz7Igm2XCnw+l+l68ZpGOR1q/O5dsRMugk68BjTgft/eGpUYhziZa5g kvCqSZwK5cABItgDLJJ9B4lHp3ePL/b0rfEiAfpdI58uc4/9b2dwSUnNnzrbhKXlKk/d s5r3CKxMsa+cOkdtaWIg3aN27quROyLUoXGktpUM5SekQLSm24wCWzJ9q58m/VXTxBn7 nEc/s98Jrjgfvn7fUZMUOjxvEHXzHxKWkgu/EcIUEBPKkONQaVs4PGvaVqPF4r8dxRGa gMM/LGrFiHfsNYGumW+HKc1qdPTH5V8aCyPOO4+VTn1SYFj2UVh42YBPLpozYrNXribv XLVg== X-Gm-Message-State: AOAM5324s8ANZ6lcGcIvs86cPB/G+LgLavND8xT46V1w5SjVh4GDro3q KE/EbIG9G6yhgI/AHP8PFsAyqwZSMEfZ X-Google-Smtp-Source: ABdhPJyYSL0q24w6bSBRKVpoN2yZQbpWZLnjfnjWLPUv3F65PWgqqpx4Vv0kdJYzyrA3HfKXiIhD5A== X-Received: by 2002:a17:90b:110a:b0:1d2:bde4:e277 with SMTP id gi10-20020a17090b110a00b001d2bde4e277mr33552950pjb.188.1651079914148; Wed, 27 Apr 2022 10:18:34 -0700 (PDT) Received: from thinkpad ([27.111.75.179]) by smtp.gmail.com with ESMTPSA id v1-20020a62c301000000b00505bc0b970dsm20234632pfg.178.2022.04.27.10.18.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Apr 2022 10:18:33 -0700 (PDT) Date: Wed, 27 Apr 2022 22:48:27 +0530 From: Manivannan Sadhasivam To: Zhi Li Cc: Frank Li , Gustavo Pimentel , hongxing.zhu@nxp.com, Lucas Stach , dl-linux-imx , linux-pci@vger.kernel.org, dmaengine@vger.kernel.org, Serge Semin , Bjorn Helgaas , Vinod Koul , Lorenzo Pieralisi , Rob Herring , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Bjorn Helgaas , Serge Semin Subject: Re: [PATCH v9 4/9] dmaengine: dw-edma: Rename wr(rd)_ch_cnt to ll_wr(rd)_cnt in struct dw_edma_chip Message-ID: <20220427171827.GD4161@thinkpad> References: <20220422143643.727871-1-Frank.Li@nxp.com> <20220422143643.727871-5-Frank.Li@nxp.com> <20220423121218.GG374560@thinkpad> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org On Sat, Apr 23, 2022 at 04:47:51PM -0500, Zhi Li wrote: > On Sat, Apr 23, 2022 at 7:12 AM Manivannan Sadhasivam > wrote: > > > > On Fri, Apr 22, 2022 at 09:36:38AM -0500, Frank Li wrote: > > > There are same name wr(rd)_ch_cnt in struct dw_edma. EDMA driver get > > > write(read) channel number from register, then save these into dw_edma. > > > Old wr(rd)_ch_cnt in dw_edma_chip actuall means how many link list memory > > > are available in ll_region_wr(rd)[EDMA_MAX_WR_CH]. So rename it to > > > ll_wr(rd)_cnt to indicate actual usage. > > > > > > Signed-off-by: Frank Li > > > > One minor comment below, > > > > Reviewed-by: Manivannan Sadhasivam > > > > > Reviewed-by: Serge Semin > > > --- > > > Change from v6 to v9 > > > - none > > > Change from v5 to v6 > > > - s/rename/Rename/ at subject > > > new patch at v4 > > > > > > drivers/dma/dw-edma/dw-edma-core.c | 4 ++-- > > > drivers/dma/dw-edma/dw-edma-pcie.c | 12 ++++++------ > > > include/linux/dma/edma.h | 8 ++++---- > > > 3 files changed, 12 insertions(+), 12 deletions(-) > > > > > > diff --git a/drivers/dma/dw-edma/dw-edma-core.c b/drivers/dma/dw-edma/dw-edma-core.c > > > index 435e4f2ab6575..1a0a98f6c5515 100644 > > > --- a/drivers/dma/dw-edma/dw-edma-core.c > > > +++ b/drivers/dma/dw-edma/dw-edma-core.c > > > @@ -919,11 +919,11 @@ int dw_edma_probe(struct dw_edma_chip *chip) > > > > > > raw_spin_lock_init(&dw->lock); > > > > > > - dw->wr_ch_cnt = min_t(u16, chip->wr_ch_cnt, > > > + dw->wr_ch_cnt = min_t(u16, chip->ll_wr_cnt, > > > dw_edma_v0_core_ch_count(dw, EDMA_DIR_WRITE)); > > > dw->wr_ch_cnt = min_t(u16, dw->wr_ch_cnt, EDMA_MAX_WR_CH); > > > > > > - dw->rd_ch_cnt = min_t(u16, chip->rd_ch_cnt, > > > + dw->rd_ch_cnt = min_t(u16, chip->ll_rd_cnt, > > > dw_edma_v0_core_ch_count(dw, EDMA_DIR_READ)); > > > dw->rd_ch_cnt = min_t(u16, dw->rd_ch_cnt, EDMA_MAX_RD_CH); > > > > > > diff --git a/drivers/dma/dw-edma/dw-edma-pcie.c b/drivers/dma/dw-edma/dw-edma-pcie.c > > > index ae42bad24dd5a..7732537f96086 100644 > > > --- a/drivers/dma/dw-edma/dw-edma-pcie.c > > > +++ b/drivers/dma/dw-edma/dw-edma-pcie.c > > > @@ -230,14 +230,14 @@ static int dw_edma_pcie_probe(struct pci_dev *pdev, > > > chip->nr_irqs = nr_irqs; > > > chip->ops = &dw_edma_pcie_core_ops; > > > > > > - chip->wr_ch_cnt = vsec_data.wr_ch_cnt; > > > - chip->rd_ch_cnt = vsec_data.rd_ch_cnt; > > > + chip->ll_wr_cnt = vsec_data.wr_ch_cnt; > > > + chip->ll_rd_cnt = vsec_data.rd_ch_cnt; > > > > > > chip->reg_base = pcim_iomap_table(pdev)[vsec_data.rg.bar]; > > > if (!chip->reg_base) > > > return -ENOMEM; > > > > > > - for (i = 0; i < chip->wr_ch_cnt; i++) { > > > + for (i = 0; i < chip->ll_wr_cnt; i++) { > > > struct dw_edma_region *ll_region = &chip->ll_region_wr[i]; > > > struct dw_edma_region *dt_region = &chip->dt_region_wr[i]; > > > struct dw_edma_block *ll_block = &vsec_data.ll_wr[i]; > > > @@ -262,7 +262,7 @@ static int dw_edma_pcie_probe(struct pci_dev *pdev, > > > dt_region->sz = dt_block->sz; > > > } > > > > > > - for (i = 0; i < chip->rd_ch_cnt; i++) { > > > + for (i = 0; i < chip->ll_rd_cnt; i++) { > > > struct dw_edma_region *ll_region = &chip->ll_region_rd[i]; > > > struct dw_edma_region *dt_region = &chip->dt_region_rd[i]; > > > struct dw_edma_block *ll_block = &vsec_data.ll_rd[i]; > > > @@ -302,7 +302,7 @@ static int dw_edma_pcie_probe(struct pci_dev *pdev, > > > chip->reg_base); > > > > > > > > > - for (i = 0; i < chip->wr_ch_cnt; i++) { > > > + for (i = 0; i < chip->ll_wr_cnt; i++) { > > > pci_dbg(pdev, "L. List:\tWRITE CH%.2u, BAR=%u, off=0x%.8lx, sz=0x%zx bytes, addr(v=%p, p=%pa)\n", > > > i, vsec_data.ll_wr[i].bar, > > > vsec_data.ll_wr[i].off, chip->ll_region_wr[i].sz, > > > @@ -314,7 +314,7 @@ static int dw_edma_pcie_probe(struct pci_dev *pdev, > > > chip->dt_region_wr[i].vaddr, &chip->dt_region_wr[i].paddr); > > > } > > > > > > - for (i = 0; i < chip->rd_ch_cnt; i++) { > > > + for (i = 0; i < chip->ll_rd_cnt; i++) { > > > pci_dbg(pdev, "L. List:\tREAD CH%.2u, BAR=%u, off=0x%.8lx, sz=0x%zx bytes, addr(v=%p, p=%pa)\n", > > > i, vsec_data.ll_rd[i].bar, > > > vsec_data.ll_rd[i].off, chip->ll_region_rd[i].sz, > > > diff --git a/include/linux/dma/edma.h b/include/linux/dma/edma.h > > > index e9ce652b88233..c2039246fc08c 100644 > > > --- a/include/linux/dma/edma.h > > > +++ b/include/linux/dma/edma.h > > > @@ -40,8 +40,8 @@ enum dw_edma_map_format { > > > * @nr_irqs: total dma irq number > > > * @ops DMA channel to IRQ number mapping > > > * @reg_base DMA register base address > > > - * @wr_ch_cnt DMA write channel number > > > - * @rd_ch_cnt DMA read channel number > > > + * @ll_wr_cnt DMA write link list number > > > + * @ll_rd_cnt DMA read link list number > > > > DMA linked list write/read memory regions? > > ll_wr_cnt is the counter of the DMA listed list. > > Do you means > > @ll_region_wr DMA linked list write memory regions > Sorry, I confused the terms here. But can you use "count" instead of "number"? Thanks, Mani > best regards > Frank Li > > > > > > Thanks, > > Mani > > > > > * @rg_region DMA register region > > > * @ll_region_wr DMA descriptor link list memory for write channel > > > * @ll_region_rd DMA descriptor link list memory for read channel > > > @@ -56,8 +56,8 @@ struct dw_edma_chip { > > > > > > void __iomem *reg_base; > > > > > > - u16 wr_ch_cnt; > > > - u16 rd_ch_cnt; > > > + u16 ll_wr_cnt; > > > + u16 ll_rd_cnt; > > > /* link list address */ > > > struct dw_edma_region ll_region_wr[EDMA_MAX_WR_CH]; > > > struct dw_edma_region ll_region_rd[EDMA_MAX_RD_CH]; > > > -- > > > 2.35.1 > > >