From: Jonathan Cameron <Jonathan.Cameron@Huawei.com>
To: <ira.weiny@intel.com>
Cc: Dan Williams <dan.j.williams@intel.com>,
Bjorn Helgaas <bhelgaas@google.com>,
Alison Schofield <alison.schofield@intel.com>,
"Vishal Verma" <vishal.l.verma@intel.com>,
Ben Widawsky <ben.widawsky@intel.com>,
<linux-kernel@vger.kernel.org>, <linux-cxl@vger.kernel.org>,
<linux-pci@vger.kernel.org>
Subject: Re: [PATCH V8 08/10] cxl/cdat: Introduce cxl_cdat_valid()
Date: Wed, 27 Apr 2022 18:56:10 +0100 [thread overview]
Message-ID: <20220427185610.0000201a@Huawei.com> (raw)
In-Reply-To: <20220414203237.2198665-9-ira.weiny@intel.com>
On Thu, 14 Apr 2022 13:32:35 -0700
ira.weiny@intel.com wrote:
> From: Ira Weiny <ira.weiny@intel.com>
>
> The CDAT data is protected by a checksum and should be the proper
> length.
>
> Introduce cxl_cdat_valid() to validate the data. While at it check and
> store the sequence number.
>
> Signed-off-by: Ira Weiny <ira.weiny@intel.com>
>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> ---
> Changes from V6
> Change name to cxl_cdat_valid() as this validates all the CDAT
> data not just the header
> Add error and debug prints
>
> Changes from V5
> New patch, split out
> Update cdat_hdr_valid()
> Remove revision and cs field parsing
> There is no point in these
> Add seq check and debug print.
> ---
> drivers/cxl/cdat.h | 2 ++
> drivers/cxl/pci.c | 36 ++++++++++++++++++++++++++++++++++++
> 2 files changed, 38 insertions(+)
>
> diff --git a/drivers/cxl/cdat.h b/drivers/cxl/cdat.h
> index 4722b6bbbaf0..a7725d26f2d2 100644
> --- a/drivers/cxl/cdat.h
> +++ b/drivers/cxl/cdat.h
> @@ -88,10 +88,12 @@
> *
> * @table: cache of CDAT table
> * @length: length of cached CDAT table
> + * @seq: Last read Sequence number of the CDAT table
> */
> struct cxl_cdat {
> void *table;
> size_t length;
> + u32 seq;
> };
>
> #endif /* !__CXL_CDAT_H__ */
> diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c
> index aecb327911a0..d7952156dd02 100644
> --- a/drivers/cxl/pci.c
> +++ b/drivers/cxl/pci.c
> @@ -781,6 +781,40 @@ static int cxl_setup_doe_devices(struct cxl_dev_state *cxlds)
> return 0;
> }
>
> +static bool cxl_cdat_valid(struct device *dev, struct cxl_cdat *cdat)
> +{
> + u32 *table = cdat->table;
> + u8 *data8 = cdat->table;
> + u32 length, seq;
> + u8 check;
> + int i;
> +
> + length = FIELD_GET(CDAT_HEADER_DW0_LENGTH, table[0]);
> + if ((length < CDAT_HEADER_LENGTH_BYTES) || (length > cdat->length)) {
> + dev_err(dev, "Invalid length %u (%lu-%lu)\n", length,
> + CDAT_HEADER_LENGTH_BYTES, cdat->length);
> + return false;
> + }
> +
> + for (check = 0, i = 0; i < length; i++)
> + check += data8[i];
> +
> + dev_dbg(dev, "CDAT length %u CS %u\n", length, check);
> + if (check != 0) {
> + dev_err(dev, "Invalid checksum %u\n", check);
> + return false;
> + }
> +
> + seq = FIELD_GET(CDAT_HEADER_DW3_SEQUENCE, table[3]);
> + /* Store the sequence for now. */
> + if (cdat->seq != seq) {
> + dev_info(dev, "CDAT seq change %x -> %x\n", cdat->seq, seq);
> + cdat->seq = seq;
> + }
> +
> + return true;
> +}
> +
> #define CDAT_DOE_REQ(entry_handle) \
> (FIELD_PREP(CXL_DOE_TABLE_ACCESS_REQ_CODE, \
> CXL_DOE_TABLE_ACCESS_REQ_CODE_READ) | \
> @@ -892,6 +926,8 @@ static int cxl_cdat_read_table(struct cxl_dev_state *cxlds,
>
> release_driver:
> cxl_pci_doe_put_drv(doe_dev);
> + if (!rc && !cxl_cdat_valid(cxlds->dev, cdat))
> + return -EIO;
> return rc;
> }
>
next prev parent reply other threads:[~2022-04-27 17:56 UTC|newest]
Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-04-14 20:32 [PATCH V8 00/10] CXL: Read CDAT and DSMAS data from the device ira.weiny
2022-04-14 20:32 ` [PATCH V8 01/10] PCI: Add vendor ID for the PCI SIG ira.weiny
2022-04-14 20:32 ` [PATCH V8 02/10] PCI: Replace magic constant for PCI Sig Vendor ID ira.weiny
2022-04-14 20:32 ` [PATCH V8 03/10] PCI: Create PCI library functions in support of DOE mailboxes ira.weiny
2022-04-28 21:27 ` Bjorn Helgaas
2022-05-02 5:36 ` ira.weiny
2022-05-30 19:06 ` Lukas Wunner
2022-05-31 10:33 ` Jonathan Cameron
2022-06-01 2:59 ` Ira Weiny
2022-06-01 7:18 ` Lukas Wunner
2022-06-01 14:23 ` Jonathan Cameron
2022-06-01 17:16 ` Ira Weiny
2022-06-01 17:56 ` Lukas Wunner
2022-06-01 20:17 ` Ira Weiny
2022-06-06 14:46 ` Jonathan Cameron
2022-06-06 19:56 ` Ira Weiny
2022-06-07 9:58 ` Jonathan Cameron
2022-05-31 23:43 ` Ira Weiny
2022-04-14 20:32 ` [PATCH V8 04/10] cxl/pci: Create auxiliary devices for each DOE mailbox ira.weiny
2022-04-27 17:19 ` Jonathan Cameron
2022-04-28 21:09 ` ira.weiny
2022-04-29 16:38 ` Jonathan Cameron
2022-04-29 17:01 ` Dan Williams
2022-05-03 16:14 ` Jonathan Cameron
2022-04-29 15:55 ` Jonathan Cameron
2022-04-29 17:20 ` Ira Weiny
2022-05-03 15:32 ` Jonathan Cameron
2022-04-14 20:32 ` [PATCH V8 05/10] cxl/pci: Create DOE auxiliary driver ira.weiny
2022-04-27 17:43 ` Jonathan Cameron
2022-04-28 14:48 ` ira.weiny
2022-04-28 15:17 ` Jonathan Cameron
2022-04-14 20:32 ` [PATCH V8 06/10] cxl/pci: Find the DOE mailbox which supports CDAT ira.weiny
2022-04-27 17:49 ` Jonathan Cameron
2022-05-09 21:25 ` Ira Weiny
2022-04-14 20:32 ` [PATCH V8 07/10] cxl/mem: Read CDAT table ira.weiny
2022-04-27 17:55 ` Jonathan Cameron
2022-04-14 20:32 ` [PATCH V8 08/10] cxl/cdat: Introduce cxl_cdat_valid() ira.weiny
2022-04-27 17:56 ` Jonathan Cameron [this message]
2022-04-14 20:32 ` [PATCH V8 09/10] cxl/mem: Retry reading CDAT on failure ira.weiny
2022-04-27 17:57 ` Jonathan Cameron
2022-04-14 20:32 ` [PATCH V8 10/10] cxl/port: Parse out DSMAS data from CDAT table ira.weiny
2022-04-27 18:01 ` Jonathan Cameron
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