Linux PCI subsystem development
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From: Bjorn Helgaas <helgaas@kernel.org>
To: Huacai Chen <chenhuacai@loongson.cn>
Cc: "Bjorn Helgaas" <bhelgaas@google.com>,
	"Lorenzo Pieralisi" <lorenzo.pieralisi@arm.com>,
	"Rob Herring" <robh@kernel.org>,
	"Krzysztof Wilczyński" <kw@linux.com>,
	linux-pci@vger.kernel.org, "Jianmin Lv" <lvjianmin@loongson.cn>,
	"Xuefeng Li" <lixuefeng@loongson.cn>,
	"Huacai Chen" <chenhuacai@gmail.com>,
	"Jiaxun Yang" <jiaxun.yang@flygoat.com>
Subject: Re: [PATCH V15 3/7] PCI: loongson: Add ACPI init support
Date: Tue, 12 Jul 2022 22:37:50 -0500	[thread overview]
Message-ID: <20220713033750.GA796301@bhelgaas> (raw)
In-Reply-To: <20220702090808.1221300-4-chenhuacai@loongson.cn>

On Sat, Jul 02, 2022 at 05:08:04PM +0800, Huacai Chen wrote:
> Loongson PCH (LS7A chipset) will be used by both MIPS-based and
> LoongArch-based Loongson processors. MIPS-based Loongson uses FDT
> while LoongArch-base Loongson uses ACPI, this patch add ACPI init
> support for the driver in drivers/pci/controller/pci-loongson.c
> because it is currently FDT-only.

> +static struct loongson_pci *pci_bus_to_loongson_pci(struct pci_bus *bus)
> +{
> +	struct pci_config_window *cfg;
> +
> +	if (acpi_disabled)
> +		return (struct loongson_pci *)(bus->sysdata);
> +	else {
> +		cfg = bus->sysdata;
> +		return (struct loongson_pci *)(cfg->priv);
> +	}

I rewrote this locally as:

  if (acpi_disabled)
    return (struct loongson_pci *)(bus->sysdata);

  cfg = bus->sysdata;
  return (struct loongson_pci *)(cfg->priv);

to avoid the asymmetry of braces/no braces.

> @@ -124,12 +138,14 @@ static void __iomem *pci_loongson_map_bus(struct pci_bus *bus, unsigned int devf
>  			       int where)
>  {
>  	unsigned char busnum = bus->number;
> -	struct pci_host_bridge *bridge = pci_find_host_bridge(bus);
> -	struct loongson_pci *priv =  pci_host_bridge_priv(bridge);
> +	struct loongson_pci *priv = pci_bus_to_loongson_pci(bus);
> +
> +	if (pci_is_root_bus(bus))
> +		busnum = 0;

I asked you about this before [1], but I don't understand the answer.

Let's say the root bus is 40 and we have this:

  40:00.0 Root Port to [bus 41]
  41:00.0 NIC

When we read the Vendor ID for 40:00.0:

  pci_loongson_map_bus(bus 40, 00.0, 0)
    if (pci_is_root_bus(bus))       # true
      busnum = 0;
    cfg0_map(priv, 0x00, 00.0, 0);
      if (bus != 0)                 # false
        ...
      addroff |= (0 << 16) | (0 << 8) | 0;

but for 41:00.0:

  pci_loongson_map_bus(bus 41, 00.0, 0)
    if (pci_is_root_bus(bus))       # false
      ...
    cfg0_map(priv, 0x41, 00.0, 0);
      if (bus != 0)                 # true
        addroff |= BIT(24);
      addroff |= (0x41 << 16) | (0 << 8) | 0;

Maybe the point is that for accesses to the root bus (which are always
Type 0 accesses), you never put "bus << 16" into addroff, no matter
what the actual root bus number is?

If that's the case, I think you should instead make cfg0_map() look
like this:

  cfg0_map(struct pci_bus *bus, ...)
  {
    unsigned long addroff = 0x0;

    if (!pci_is_root_bus(bus)) {
      addroff |= BIT(24);
      addroff |= (bus << 16);
    }
    addroff |= (devfn << 8) | where;
    return priv->cfg0_base + addroff;
  }

Then you don't need to do the weird busnum override in
pci_loongson_map_bus(), and the root bus checking is in one place
(cfg0_map()) instead of being split between pci_loongson_map_bus() and
cfg0_map().  Same for cfg1_map(), obviously.

[1] https://lore.kernel.org/r/20220531230437.GA793965@bhelgaas

  reply	other threads:[~2022-07-13  3:37 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-07-02  9:08 [PATCH V15 0/7] PCI: Loongson pci improvements and quirks Huacai Chen
2022-07-02  9:08 ` [PATCH V15 1/7] PCI/ACPI: Guard ARM64-specific mcfg_quirks Huacai Chen
2022-07-02  9:08 ` [PATCH V15 2/7] PCI: loongson: Use generic 8/16/32-bit config ops on LS2K/LS7A Huacai Chen
2022-07-02  9:08 ` [PATCH V15 3/7] PCI: loongson: Add ACPI init support Huacai Chen
2022-07-13  3:37   ` Bjorn Helgaas [this message]
2022-07-13 11:48     ` Jianmin Lv
2022-07-02  9:08 ` [PATCH V15 4/7] PCI: loongson: Don't access non-existant devices Huacai Chen
2022-07-02  9:08 ` [PATCH V15 5/7] PCI: loongson: Improve the MRRS quirk for LS7A Huacai Chen
2022-07-13 17:42   ` Bjorn Helgaas
2022-07-14  6:13     ` Jianmin Lv
2022-07-02  9:08 ` [PATCH V15 6/7] PCI: Add quirk for LS7A to avoid reboot failure Huacai Chen
2022-07-02  9:08 ` [PATCH V15 7/7] PCI: Add quirk for multifunction devices of LS7A Huacai Chen

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