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Bolarinwa" , Rajat Jain , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , helgaas@kernel.org Subject: Re: [PATCH v5] PCI/ASPM: Update LTR threshold based upon reported max latencies Message-ID: <20220715082852.GC12197@workstation> References: <1654242861-15695-1-git-send-email-quic_krichai@quicinc.com> <1654837710-30561-1-git-send-email-quic_krichai@quicinc.com> <20f88022-e9b1-53b3-8832-85edc713ef6a@quicinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20f88022-e9b1-53b3-8832-85edc713ef6a@quicinc.com> User-Agent: Mutt/1.9.4 (2018-02-28) Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org On Wed, Jun 15, 2022 at 06:53:18PM +0530, Krishna Chaitanya Chundru wrote: > A Gentle remainder please review it. > > On 6/10/2022 10:38 AM, Krishna chaitanya chundru wrote: > > From: Prasad Malisetty > > > > In ASPM driver, LTR threshold scale and value are updated based on > > tcommon_mode and t_poweron values. In kioxia NVMe L1.2 is failing due to > > LTR threshold scale and value are greater values than max snoop/non-snoop > > value. > > > > Based on PCIe r4.1, sec 5.5.1, L1.2 substate must be entered when > > reported snoop/no-snoop values is greather than or equal to > > LTR_L1.2_THRESHOLD value. > > > > Signed-off-by: Prasad Malisetty > > Signed-off-by: Krishna chaitanya chundru As Stephen noted in previous verison, you should sent the newer versions separately and not as a reply to previous ones. So please sent v6 with my tag as well. Thanks, Mani > > --- > > > > I am taking this patch forward as prasad is no more working with our org. > > Changes since v4: > > - Replaced conditional statements with min and max. > > changes since v3: > > - Changed the logic to include this condition "snoop/nosnoop > > latencies are not equal to zero and lower than LTR_L1.2_THRESHOLD" > > Changes since v2: > > - Replaced LTRME logic with max snoop/no-snoop latencies check. > > Changes since v1: > > - Added missing variable declaration in v1 patch > > --- > > drivers/pci/pcie/aspm.c | 30 ++++++++++++++++++++++++++++++ > > 1 file changed, 30 insertions(+) > > > > diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c > > index a96b742..676c03e 100644 > > --- a/drivers/pci/pcie/aspm.c > > +++ b/drivers/pci/pcie/aspm.c > > @@ -461,14 +461,36 @@ static void aspm_calc_l1ss_info(struct pcie_link_state *link, > > { > > struct pci_dev *child = link->downstream, *parent = link->pdev; > > u32 val1, val2, scale1, scale2; > > + u32 max_val, max_scale, max_snp_scale, max_snp_val, max_nsnp_scale, max_nsnp_val; > > u32 t_common_mode, t_power_on, l1_2_threshold, scale, value; > > u32 ctl1 = 0, ctl2 = 0; > > u32 pctl1, pctl2, cctl1, cctl2; > > u32 pl1_2_enables, cl1_2_enables; > > + u16 ltr; > > + u16 max_snoop_lat, max_nosnoop_lat; > > if (!(link->aspm_support & ASPM_STATE_L1_2_MASK)) > > return; > > + ltr = pci_find_ext_capability(child, PCI_EXT_CAP_ID_LTR); > > + if (!ltr) > > + return; > > + > > + pci_read_config_word(child, ltr + PCI_LTR_MAX_SNOOP_LAT, &max_snoop_lat); > > + pci_read_config_word(child, ltr + PCI_LTR_MAX_NOSNOOP_LAT, &max_nosnoop_lat); > > + > > + max_snp_scale = (max_snoop_lat & PCI_LTR_SCALE_MASK) >> PCI_LTR_SCALE_SHIFT; > > + max_snp_val = max_snoop_lat & PCI_LTR_VALUE_MASK; > > + > > + max_nsnp_scale = (max_nosnoop_lat & PCI_LTR_SCALE_MASK) >> PCI_LTR_SCALE_SHIFT; > > + max_nsnp_val = max_nosnoop_lat & PCI_LTR_VALUE_MASK; > > + > > + /* choose the greater max scale value between snoop and no snoop value*/ > > + max_scale = max(max_snp_scale, max_nsnp_scale); > > + > > + /* choose the greater max value between snoop and no snoop scales */ > > + max_val = max(max_snp_val, max_nsnp_val); > > + > > /* Choose the greater of the two Port Common_Mode_Restore_Times */ > > val1 = (parent_l1ss_cap & PCI_L1SS_CAP_CM_RESTORE_TIME) >> 8; > > val2 = (child_l1ss_cap & PCI_L1SS_CAP_CM_RESTORE_TIME) >> 8; > > @@ -501,6 +523,14 @@ static void aspm_calc_l1ss_info(struct pcie_link_state *link, > > */ > > l1_2_threshold = 2 + 4 + t_common_mode + t_power_on; > > encode_l12_threshold(l1_2_threshold, &scale, &value); > > + > > + /* > > + * Based on PCIe r4.1, sec 5.5.1, L1.2 substate must be entered when reported > > + * snoop/no-snoop values are greather than or equal to LTR_L1.2_THRESHOLD value. > > + */ > > + scale = min(scale, max_scale); > > + value = min(value, max_val); > > + > > ctl1 |= t_common_mode << 8 | scale << 29 | value << 16; > > /* Some broken devices only support dword access to L1 SS */