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Fri, 29 Jul 2022 15:53:22 -0700 (PDT) Received: (nullmailer pid 87726 invoked by uid 1000); Fri, 29 Jul 2022 22:53:20 -0000 Date: Fri, 29 Jul 2022 16:53:20 -0600 From: Rob Herring To: Jianjun Wang Cc: Bjorn Helgaas , Krzysztof Kozlowski , Matthias Brugger , linux-pci@vger.kernel.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Ryder Lee , Rex-BC.Chen@mediatek.com, TingHan.Shen@mediatek.com, Liju-clr.Chen@mediatek.com, Jian.Yang@mediatek.com Subject: Re: [PATCH v2] dt-bindings: PCI: mediatek-gen3: Add support for MT8188 and MT8195 Message-ID: <20220729225320.GA82746-robh@kernel.org> References: <20220729033331.3075-1-jianjun.wang@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20220729033331.3075-1-jianjun.wang@mediatek.com> Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org On Fri, Jul 29, 2022 at 11:33:31AM +0800, Jianjun Wang wrote: > MT8188 and MT8195 are ARM platform SoCs with the same PCIe IP as MT8192. > > Also add new clock name "peri_mem" since the MT8188 and MT8195 use clock > "peri_mem" instead of "top_133m". > > Signed-off-by: Jianjun Wang > --- > Changes in v2: > Merge two patches into one. > --- > .../bindings/pci/mediatek-pcie-gen3.yaml | 51 +++++++++++++++---- > 1 file changed, 40 insertions(+), 11 deletions(-) > > diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml > index 0499b94627ae..038e25ae0be7 100644 > --- a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml > +++ b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml > @@ -43,12 +43,16 @@ description: |+ > each set has its own address for MSI message, and supports 32 MSI vectors > to generate interrupt. > > -allOf: > - - $ref: /schemas/pci/pci-bus.yaml# > - > properties: > compatible: > - const: mediatek,mt8192-pcie > + oneOf: > + - items: > + - enum: > + - mediatek,mt8188-pcie > + - mediatek,mt8195-pcie > + - const: mediatek,mt8192-pcie > + - items: > + - const: mediatek,mt8192-pcie > > reg: > maxItems: 1 > @@ -78,13 +82,7 @@ properties: > maxItems: 6 > > clock-names: > - items: > - - const: pl_250m > - - const: tl_26m > - - const: tl_96m > - - const: tl_32k > - - const: peri_26m > - - const: top_133m > + maxItems: 6 > > assigned-clocks: > maxItems: 1 > @@ -126,9 +124,40 @@ required: > - interrupts > - ranges > - clocks > + - clock-names > - '#interrupt-cells' > - interrupt-controller > > +allOf: > + - $ref: /schemas/pci/pci-bus.yaml# > + - if: > + properties: > + compatible: > + contains: > + enum: > + - mediatek,mt8188-pcie > + - mediatek,mt8195-pcie > + then: > + properties: > + clock-names: > + items: > + - const: pl_250m > + - const: tl_26m > + - const: tl_96m > + - const: tl_32k > + - const: peri_26m > + - const: peri_mem > + else: > + properties: > + clock-names: > + items: > + - const: pl_250m > + - const: tl_26m > + - const: tl_96m > + - const: tl_32k > + - const: peri_26m > + - const: top_133m I'm not sure it's worth enforcing just the last clock name. Just do: enum: [ peri_mem, top_133m ] And key in the top level. Rob