From: Vidya Sagar <vidyas@nvidia.com>
To: <jingoohan1@gmail.com>, <gustavo.pimentel@synopsys.com>,
<lpieralisi@kernel.org>, <robh@kernel.org>, <kw@linux.com>,
<bhelgaas@google.com>
Cc: <linux-pci@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<kthota@nvidia.com>, <mmaddireddy@nvidia.com>,
<vidyas@nvidia.com>, <sagar.tv@gmail.com>
Subject: [PATCH V1 1/2] PCI: Add PCI_PTM_CAP_RES macro
Date: Mon, 19 Sep 2022 20:03:39 +0530 [thread overview]
Message-ID: <20220919143340.4527-2-vidyas@nvidia.com> (raw)
In-Reply-To: <20220919143340.4527-1-vidyas@nvidia.com>
Add macro defining Responder capable bit in Precision Time Measurement
capability register.
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
---
include/uapi/linux/pci_regs.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
index 57b8e2ffb1dd..1c3591c8e09e 100644
--- a/include/uapi/linux/pci_regs.h
+++ b/include/uapi/linux/pci_regs.h
@@ -1058,6 +1058,7 @@
/* Precision Time Measurement */
#define PCI_PTM_CAP 0x04 /* PTM Capability */
#define PCI_PTM_CAP_REQ 0x00000001 /* Requester capable */
+#define PCI_PTM_CAP_RES 0x00000002 /* Responder capable */
#define PCI_PTM_CAP_ROOT 0x00000004 /* Root capable */
#define PCI_PTM_GRANULARITY_MASK 0x0000FF00 /* Clock granularity */
#define PCI_PTM_CTRL 0x08 /* PTM Control */
--
2.17.1
next prev parent reply other threads:[~2022-09-19 14:34 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-19 14:33 [PATCH V1 0/2] Disable PTM for endpoint mode Vidya Sagar
2022-09-19 14:33 ` Vidya Sagar [this message]
2022-09-23 21:37 ` [PATCH V1 1/2] PCI: Add PCI_PTM_CAP_RES macro Han Jingoo
2022-09-19 14:33 ` [PATCH V1 2/2] PCI: designware-ep: Disable PTM capabilities for EP mode Vidya Sagar
2022-09-23 21:40 ` Han Jingoo
2022-10-27 11:32 ` Lorenzo Pieralisi
2022-10-27 20:17 ` Han Jingoo
2022-10-28 16:57 ` Bjorn Helgaas
2022-10-27 12:45 ` [PATCH V1 0/2] Disable PTM for endpoint mode Lorenzo Pieralisi
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