From: Thomas Gleixner <tglx@linutronix.de>
To: LKML <linux-kernel@vger.kernel.org>
Cc: x86@kernel.org, Joerg Roedel <joro@8bytes.org>,
Will Deacon <will@kernel.org>,
linux-pci@vger.kernel.org, Bjorn Helgaas <bhelgaas@google.com>,
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
Marc Zyngier <maz@kernel.org>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
Jason Gunthorpe <jgg@mellanox.com>,
Dave Jiang <dave.jiang@intel.com>,
Alex Williamson <alex.williamson@redhat.com>,
Kevin Tian <kevin.tian@intel.com>,
Dan Williams <dan.j.williams@intel.com>,
Logan Gunthorpe <logang@deltatee.com>,
Ashok Raj <ashok.raj@intel.com>, Jon Mason <jdmason@kudzu.us>,
Allen Hubbe <allenbh@gmail.com>
Subject: [patch V2 09/33] genirq/msi: Add range checking to msi_insert_desc()
Date: Mon, 21 Nov 2022 15:37:57 +0100 (CET) [thread overview]
Message-ID: <20221121091326.997114715@linutronix.de> (raw)
In-Reply-To: 20221121083657.157152924@linutronix.de
Per device domains provide the domain size to the core code. This allows
range checking on insertion of MSI descriptors and also paves the way for
dynamic index allocations which are required e.g. for IMS. This avoids
external mechanisms like bitmaps on the device side and just utilizes
the core internal MSI descriptor store for it.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
---
kernel/irq/msi.c | 40 +++++++++++++++++++++++++++++++++++-----
1 file changed, 35 insertions(+), 5 deletions(-)
--- a/kernel/irq/msi.c
+++ b/kernel/irq/msi.c
@@ -74,6 +74,7 @@ static int msi_get_domain_base_index(str
return domid * MSI_XA_DOMAIN_SIZE;
}
+static unsigned int msi_domain_get_hwsize(struct device *dev, unsigned int domid);
/**
* msi_alloc_desc - Allocate an initialized msi_desc
@@ -116,6 +117,7 @@ static int msi_insert_desc(struct device
unsigned int domid, unsigned int index)
{
struct msi_device_data *md = dev->msi.data;
+ unsigned int hwsize;
int baseidx, ret;
baseidx = msi_get_domain_base_index(dev, domid);
@@ -124,6 +126,12 @@ static int msi_insert_desc(struct device
goto fail;
}
+ hwsize = msi_domain_get_hwsize(dev, domid);
+ if (index >= hwsize) {
+ ret = -ERANGE;
+ goto fail;
+ }
+
desc->msi_index = index;
index += baseidx;
ret = xa_insert(&md->__store, index, desc, GFP_KERNEL);
@@ -179,9 +187,11 @@ static bool msi_desc_match(struct msi_de
static bool msi_ctrl_range_valid(struct device *dev, struct msi_ctrl *ctrl)
{
+ unsigned int hwsize = msi_domain_get_hwsize(dev, ctrl->domid);
+
if (WARN_ON_ONCE(ctrl->first > ctrl->last ||
- ctrl->first > MSI_MAX_INDEX ||
- ctrl->last > MSI_MAX_INDEX))
+ ctrl->first >= hwsize ||
+ ctrl->last >= hwsize))
return false;
return true;
}
@@ -446,7 +456,7 @@ unsigned int msi_domain_get_virq(struct
if (!dev->msi.data)
return 0;
- if (WARN_ON_ONCE(index > MSI_MAX_INDEX))
+ if (WARN_ON_ONCE(index >= msi_domain_get_hwsize(dev, domid)))
return 0;
/* This check is only valid for the PCI default MSI domain */
@@ -614,6 +624,25 @@ static struct irq_domain *msi_get_device
return domain;
}
+static unsigned int msi_domain_get_hwsize(struct device *dev, unsigned int domid)
+{
+ struct msi_domain_info *info;
+ struct irq_domain *domain;
+
+ /*
+ * Retrieve the MSI domain for range checking. If there is no
+ * domain or the domain is not a per device domain, then assume
+ * full MSI range and pray that the calling subsystem knows what it
+ * is doing.
+ */
+ domain = msi_get_device_domain(dev, domid);
+ if (domain && irq_domain_is_msi_device(domain)) {
+ info = domain->host_data;
+ return info->hwsize;
+ }
+ return MSI_MAX_INDEX + 1;
+}
+
static inline void irq_chip_write_msi_msg(struct irq_data *data,
struct msi_msg *msg)
{
@@ -1390,7 +1419,7 @@ int msi_domain_alloc_irqs_all_locked(str
struct msi_ctrl ctrl = {
.domid = domid,
.first = 0,
- .last = MSI_MAX_INDEX,
+ .last = msi_domain_get_hwsize(dev, domid) - 1,
.nirqs = nirqs,
};
@@ -1506,7 +1535,8 @@ void msi_domain_free_irqs_range(struct d
*/
void msi_domain_free_irqs_all_locked(struct device *dev, unsigned int domid)
{
- msi_domain_free_irqs_range_locked(dev, domid, 0, MSI_MAX_INDEX);
+ msi_domain_free_irqs_range_locked(dev, domid, 0,
+ msi_domain_get_hwsize(dev, domid) - 1);
}
/**
next prev parent reply other threads:[~2022-11-21 14:38 UTC|newest]
Thread overview: 71+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-21 14:37 [patch V2 00/33] genirq, PCI/MSI: Support for per device MSI and PCI/IMS - Part 3 implementation Thomas Gleixner
2022-11-21 14:37 ` [patch V2 01/33] genirq/msi: Rearrange MSI domain flags Thomas Gleixner
2022-11-21 14:37 ` [patch V2 02/33] genirq/msi: Provide struct msi_parent_ops Thomas Gleixner
2022-11-23 7:57 ` Tian, Kevin
2022-11-23 11:28 ` Thomas Gleixner
2022-11-24 0:53 ` Tian, Kevin
2022-11-21 14:37 ` [patch V2 03/33] genirq/msi: Provide data structs for per device domains Thomas Gleixner
2022-11-23 7:57 ` Tian, Kevin
2022-11-23 11:29 ` Thomas Gleixner
2022-11-21 14:37 ` [patch V2 04/33] genirq/msi: Add size info to struct msi_domain_info Thomas Gleixner
2022-11-21 14:37 ` [patch V2 05/33] genirq/msi: Split msi_create_irq_domain() Thomas Gleixner
2022-11-21 14:37 ` [patch V2 06/33] genirq/irqdomain: Add irq_domain::dev for per device MSI domains Thomas Gleixner
2022-11-21 14:37 ` [patch V2 07/33] genirq/msi: Provide msi_create/free_device_irq_domain() Thomas Gleixner
2022-11-23 8:02 ` Tian, Kevin
2022-11-23 11:38 ` Thomas Gleixner
2022-11-23 21:01 ` Thomas Gleixner
2022-11-24 1:07 ` Tian, Kevin
2022-11-24 8:36 ` Thomas Gleixner
2022-11-28 1:47 ` Tian, Kevin
2022-11-21 14:37 ` [patch V2 08/33] genirq/msi: Provide msi_match_device_domain() Thomas Gleixner
2022-11-21 14:37 ` Thomas Gleixner [this message]
2022-11-21 14:37 ` [patch V2 10/33] PCI/MSI: Split __pci_write_msi_msg() Thomas Gleixner
2022-11-21 14:37 ` [patch V2 11/33] genirq/msi: Provide BUS_DEVICE_PCI_MSI[X] Thomas Gleixner
2022-11-21 14:38 ` [patch V2 12/33] PCI/MSI: Add support for per device MSI[X] domains Thomas Gleixner
2022-11-23 8:08 ` Tian, Kevin
2022-11-23 11:41 ` Thomas Gleixner
2022-11-23 21:50 ` Thomas Gleixner
2022-11-24 1:08 ` Tian, Kevin
2022-11-21 14:38 ` [patch V2 13/33] x86/apic/vector: Provide MSI parent domain Thomas Gleixner
2022-11-23 8:16 ` Tian, Kevin
2022-11-23 13:42 ` Thomas Gleixner
2022-11-24 1:10 ` Tian, Kevin
2022-11-21 14:38 ` [patch V2 14/33] PCI/MSI: Remove unused pci_dev_has_special_msi_domain() Thomas Gleixner
2022-11-21 14:38 ` [patch V2 15/33] iommu/vt-d: Switch to MSI parent domains Thomas Gleixner
2022-11-21 14:38 ` [patch V2 16/33] iommu/amd: Switch to MSI base domains Thomas Gleixner
2022-11-21 14:38 ` [patch V2 17/33] x86/apic/msi: Remove arch_create_remap_msi_irq_domain() Thomas Gleixner
2022-11-21 14:38 ` [patch V2 18/33] genirq/msi: Provide struct msi_map Thomas Gleixner
2022-11-21 14:38 ` [patch V2 19/33] genirq/msi: Provide msi_desc::msi_data Thomas Gleixner
2022-11-23 8:27 ` Tian, Kevin
2022-11-23 11:41 ` Thomas Gleixner
2022-11-21 14:38 ` [patch V2 20/33] genirq/msi: Provide msi_domain_ops::prepare_desc() Thomas Gleixner
2022-11-21 14:38 ` [patch V2 21/33] genirq/msi: Provide msi_domain_alloc_irq_at() Thomas Gleixner
2022-11-24 2:54 ` Tian, Kevin
2022-11-21 14:38 ` [patch V2 22/33] genirq/msi: Provide MSI_FLAG_MSIX_ALLOC_DYN Thomas Gleixner
2022-11-21 14:38 ` [patch V2 23/33] PCI/MSI: Split MSI-X descriptor setup Thomas Gleixner
2022-11-21 14:38 ` [patch V2 24/33] PCI/MSI: Provide prepare_desc() MSI domain op Thomas Gleixner
2022-11-21 14:38 ` [patch V2 25/33] PCI/MSI: Provide post-enable dynamic allocation interfaces for MSI-X Thomas Gleixner
2022-11-24 2:58 ` Tian, Kevin
2022-11-24 9:08 ` Thomas Gleixner
2022-11-28 1:49 ` Tian, Kevin
2022-11-21 14:38 ` [patch V2 26/33] x86/apic/msi: Enable MSI_FLAG_PCI_MSIX_ALLOC_DYN Thomas Gleixner
2022-11-21 14:38 ` [patch V2 27/33] genirq/msi: Provide constants for PCI/IMS support Thomas Gleixner
2022-11-24 3:01 ` Tian, Kevin
2022-11-24 9:10 ` Thomas Gleixner
2022-11-24 13:09 ` Jason Gunthorpe
2022-11-24 13:28 ` Thomas Gleixner
2022-11-21 14:38 ` [patch V2 28/33] PCI/MSI: Provide IMS (Interrupt Message Store) support Thomas Gleixner
2022-11-24 3:10 ` Tian, Kevin
2022-11-24 9:10 ` Thomas Gleixner
2022-11-21 14:38 ` [patch V2 29/33] PCI/MSI: Provide pci_ims_alloc/free_irq() Thomas Gleixner
2022-11-24 3:11 ` Tian, Kevin
2022-11-21 14:38 ` [patch V2 30/33] x86/apic/msi: Enable PCI/IMS Thomas Gleixner
2022-11-21 14:38 ` [patch V2 31/33] iommu/vt-d: " Thomas Gleixner
2022-11-24 3:17 ` Tian, Kevin
2022-11-24 9:37 ` Thomas Gleixner
2022-11-24 13:14 ` Jason Gunthorpe
2022-11-24 13:21 ` Thomas Gleixner
2022-11-28 1:54 ` Tian, Kevin
2022-11-21 14:38 ` [patch V2 32/33] iommu/amd: " Thomas Gleixner
2022-11-21 14:38 ` [patch V2 33/33] irqchip: Add IDXD Interrupt Message Store driver Thomas Gleixner
2022-11-24 3:19 ` Tian, Kevin
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