From: Thomas Gleixner <tglx@linutronix.de>
To: LKML <linux-kernel@vger.kernel.org>
Cc: x86@kernel.org, Joerg Roedel <joro@8bytes.org>,
Will Deacon <will@kernel.org>,
linux-pci@vger.kernel.org, Bjorn Helgaas <bhelgaas@google.com>,
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
Marc Zyngier <maz@kernel.org>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
Jason Gunthorpe <jgg@mellanox.com>,
Dave Jiang <dave.jiang@intel.com>,
Alex Williamson <alex.williamson@redhat.com>,
Kevin Tian <kevin.tian@intel.com>,
Dan Williams <dan.j.williams@intel.com>,
Logan Gunthorpe <logang@deltatee.com>,
Ashok Raj <ashok.raj@intel.com>, Jon Mason <jdmason@kudzu.us>,
Allen Hubbe <allenbh@gmail.com>,
"Ahmed S. Darwish" <darwi@linutronix.de>
Subject: [patch V2 10/33] PCI/MSI: Split __pci_write_msi_msg()
Date: Mon, 21 Nov 2022 15:37:58 +0100 (CET) [thread overview]
Message-ID: <20221121091327.052582141@linutronix.de> (raw)
In-Reply-To: 20221121083657.157152924@linutronix.de
The upcoming per device MSI domains will create different domains for MSI
and MSI-X. Split the write message function into MSI and MSI-X helpers so
they can be used by those new domain functions seperately.
Signed-off-by: Ahmed S. Darwish <darwi@linutronix.de>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
---
drivers/pci/msi/msi.c | 104 +++++++++++++++++++++++++-------------------------
1 file changed, 54 insertions(+), 50 deletions(-)
--- a/drivers/pci/msi/msi.c
+++ b/drivers/pci/msi/msi.c
@@ -180,6 +180,58 @@ void __pci_read_msi_msg(struct msi_desc
}
}
+static inline void pci_write_msg_msi(struct pci_dev *dev, struct msi_desc *desc,
+ struct msi_msg *msg)
+{
+ int pos = dev->msi_cap;
+ u16 msgctl;
+
+ pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &msgctl);
+ msgctl &= ~PCI_MSI_FLAGS_QSIZE;
+ msgctl |= desc->pci.msi_attrib.multiple << 4;
+ pci_write_config_word(dev, pos + PCI_MSI_FLAGS, msgctl);
+
+ pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_LO, msg->address_lo);
+ if (desc->pci.msi_attrib.is_64) {
+ pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_HI, msg->address_hi);
+ pci_write_config_word(dev, pos + PCI_MSI_DATA_64, msg->data);
+ } else {
+ pci_write_config_word(dev, pos + PCI_MSI_DATA_32, msg->data);
+ }
+ /* Ensure that the writes are visible in the device */
+ pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &msgctl);
+}
+
+static inline void pci_write_msg_msix(struct msi_desc *desc, struct msi_msg *msg)
+{
+ void __iomem *base = pci_msix_desc_addr(desc);
+ u32 ctrl = desc->pci.msix_ctrl;
+ bool unmasked = !(ctrl & PCI_MSIX_ENTRY_CTRL_MASKBIT);
+
+ if (desc->pci.msi_attrib.is_virtual)
+ return;
+ /*
+ * The specification mandates that the entry is masked
+ * when the message is modified:
+ *
+ * "If software changes the Address or Data value of an
+ * entry while the entry is unmasked, the result is
+ * undefined."
+ */
+ if (unmasked)
+ pci_msix_write_vector_ctrl(desc, ctrl | PCI_MSIX_ENTRY_CTRL_MASKBIT);
+
+ writel(msg->address_lo, base + PCI_MSIX_ENTRY_LOWER_ADDR);
+ writel(msg->address_hi, base + PCI_MSIX_ENTRY_UPPER_ADDR);
+ writel(msg->data, base + PCI_MSIX_ENTRY_DATA);
+
+ if (unmasked)
+ pci_msix_write_vector_ctrl(desc, ctrl);
+
+ /* Ensure that the writes are visible in the device */
+ readl(base + PCI_MSIX_ENTRY_DATA);
+}
+
void __pci_write_msi_msg(struct msi_desc *entry, struct msi_msg *msg)
{
struct pci_dev *dev = msi_desc_to_pci_dev(entry);
@@ -187,63 +239,15 @@ void __pci_write_msi_msg(struct msi_desc
if (dev->current_state != PCI_D0 || pci_dev_is_disconnected(dev)) {
/* Don't touch the hardware now */
} else if (entry->pci.msi_attrib.is_msix) {
- void __iomem *base = pci_msix_desc_addr(entry);
- u32 ctrl = entry->pci.msix_ctrl;
- bool unmasked = !(ctrl & PCI_MSIX_ENTRY_CTRL_MASKBIT);
-
- if (entry->pci.msi_attrib.is_virtual)
- goto skip;
-
- /*
- * The specification mandates that the entry is masked
- * when the message is modified:
- *
- * "If software changes the Address or Data value of an
- * entry while the entry is unmasked, the result is
- * undefined."
- */
- if (unmasked)
- pci_msix_write_vector_ctrl(entry, ctrl | PCI_MSIX_ENTRY_CTRL_MASKBIT);
-
- writel(msg->address_lo, base + PCI_MSIX_ENTRY_LOWER_ADDR);
- writel(msg->address_hi, base + PCI_MSIX_ENTRY_UPPER_ADDR);
- writel(msg->data, base + PCI_MSIX_ENTRY_DATA);
-
- if (unmasked)
- pci_msix_write_vector_ctrl(entry, ctrl);
-
- /* Ensure that the writes are visible in the device */
- readl(base + PCI_MSIX_ENTRY_DATA);
+ pci_write_msg_msix(entry, msg);
} else {
- int pos = dev->msi_cap;
- u16 msgctl;
-
- pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &msgctl);
- msgctl &= ~PCI_MSI_FLAGS_QSIZE;
- msgctl |= entry->pci.msi_attrib.multiple << 4;
- pci_write_config_word(dev, pos + PCI_MSI_FLAGS, msgctl);
-
- pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_LO,
- msg->address_lo);
- if (entry->pci.msi_attrib.is_64) {
- pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_HI,
- msg->address_hi);
- pci_write_config_word(dev, pos + PCI_MSI_DATA_64,
- msg->data);
- } else {
- pci_write_config_word(dev, pos + PCI_MSI_DATA_32,
- msg->data);
- }
- /* Ensure that the writes are visible in the device */
- pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &msgctl);
+ pci_write_msg_msi(dev, entry, msg);
}
-skip:
entry->msg = *msg;
if (entry->write_msi_msg)
entry->write_msi_msg(entry, entry->write_msi_msg_data);
-
}
void pci_write_msi_msg(unsigned int irq, struct msi_msg *msg)
next prev parent reply other threads:[~2022-11-21 14:38 UTC|newest]
Thread overview: 71+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-21 14:37 [patch V2 00/33] genirq, PCI/MSI: Support for per device MSI and PCI/IMS - Part 3 implementation Thomas Gleixner
2022-11-21 14:37 ` [patch V2 01/33] genirq/msi: Rearrange MSI domain flags Thomas Gleixner
2022-11-21 14:37 ` [patch V2 02/33] genirq/msi: Provide struct msi_parent_ops Thomas Gleixner
2022-11-23 7:57 ` Tian, Kevin
2022-11-23 11:28 ` Thomas Gleixner
2022-11-24 0:53 ` Tian, Kevin
2022-11-21 14:37 ` [patch V2 03/33] genirq/msi: Provide data structs for per device domains Thomas Gleixner
2022-11-23 7:57 ` Tian, Kevin
2022-11-23 11:29 ` Thomas Gleixner
2022-11-21 14:37 ` [patch V2 04/33] genirq/msi: Add size info to struct msi_domain_info Thomas Gleixner
2022-11-21 14:37 ` [patch V2 05/33] genirq/msi: Split msi_create_irq_domain() Thomas Gleixner
2022-11-21 14:37 ` [patch V2 06/33] genirq/irqdomain: Add irq_domain::dev for per device MSI domains Thomas Gleixner
2022-11-21 14:37 ` [patch V2 07/33] genirq/msi: Provide msi_create/free_device_irq_domain() Thomas Gleixner
2022-11-23 8:02 ` Tian, Kevin
2022-11-23 11:38 ` Thomas Gleixner
2022-11-23 21:01 ` Thomas Gleixner
2022-11-24 1:07 ` Tian, Kevin
2022-11-24 8:36 ` Thomas Gleixner
2022-11-28 1:47 ` Tian, Kevin
2022-11-21 14:37 ` [patch V2 08/33] genirq/msi: Provide msi_match_device_domain() Thomas Gleixner
2022-11-21 14:37 ` [patch V2 09/33] genirq/msi: Add range checking to msi_insert_desc() Thomas Gleixner
2022-11-21 14:37 ` Thomas Gleixner [this message]
2022-11-21 14:37 ` [patch V2 11/33] genirq/msi: Provide BUS_DEVICE_PCI_MSI[X] Thomas Gleixner
2022-11-21 14:38 ` [patch V2 12/33] PCI/MSI: Add support for per device MSI[X] domains Thomas Gleixner
2022-11-23 8:08 ` Tian, Kevin
2022-11-23 11:41 ` Thomas Gleixner
2022-11-23 21:50 ` Thomas Gleixner
2022-11-24 1:08 ` Tian, Kevin
2022-11-21 14:38 ` [patch V2 13/33] x86/apic/vector: Provide MSI parent domain Thomas Gleixner
2022-11-23 8:16 ` Tian, Kevin
2022-11-23 13:42 ` Thomas Gleixner
2022-11-24 1:10 ` Tian, Kevin
2022-11-21 14:38 ` [patch V2 14/33] PCI/MSI: Remove unused pci_dev_has_special_msi_domain() Thomas Gleixner
2022-11-21 14:38 ` [patch V2 15/33] iommu/vt-d: Switch to MSI parent domains Thomas Gleixner
2022-11-21 14:38 ` [patch V2 16/33] iommu/amd: Switch to MSI base domains Thomas Gleixner
2022-11-21 14:38 ` [patch V2 17/33] x86/apic/msi: Remove arch_create_remap_msi_irq_domain() Thomas Gleixner
2022-11-21 14:38 ` [patch V2 18/33] genirq/msi: Provide struct msi_map Thomas Gleixner
2022-11-21 14:38 ` [patch V2 19/33] genirq/msi: Provide msi_desc::msi_data Thomas Gleixner
2022-11-23 8:27 ` Tian, Kevin
2022-11-23 11:41 ` Thomas Gleixner
2022-11-21 14:38 ` [patch V2 20/33] genirq/msi: Provide msi_domain_ops::prepare_desc() Thomas Gleixner
2022-11-21 14:38 ` [patch V2 21/33] genirq/msi: Provide msi_domain_alloc_irq_at() Thomas Gleixner
2022-11-24 2:54 ` Tian, Kevin
2022-11-21 14:38 ` [patch V2 22/33] genirq/msi: Provide MSI_FLAG_MSIX_ALLOC_DYN Thomas Gleixner
2022-11-21 14:38 ` [patch V2 23/33] PCI/MSI: Split MSI-X descriptor setup Thomas Gleixner
2022-11-21 14:38 ` [patch V2 24/33] PCI/MSI: Provide prepare_desc() MSI domain op Thomas Gleixner
2022-11-21 14:38 ` [patch V2 25/33] PCI/MSI: Provide post-enable dynamic allocation interfaces for MSI-X Thomas Gleixner
2022-11-24 2:58 ` Tian, Kevin
2022-11-24 9:08 ` Thomas Gleixner
2022-11-28 1:49 ` Tian, Kevin
2022-11-21 14:38 ` [patch V2 26/33] x86/apic/msi: Enable MSI_FLAG_PCI_MSIX_ALLOC_DYN Thomas Gleixner
2022-11-21 14:38 ` [patch V2 27/33] genirq/msi: Provide constants for PCI/IMS support Thomas Gleixner
2022-11-24 3:01 ` Tian, Kevin
2022-11-24 9:10 ` Thomas Gleixner
2022-11-24 13:09 ` Jason Gunthorpe
2022-11-24 13:28 ` Thomas Gleixner
2022-11-21 14:38 ` [patch V2 28/33] PCI/MSI: Provide IMS (Interrupt Message Store) support Thomas Gleixner
2022-11-24 3:10 ` Tian, Kevin
2022-11-24 9:10 ` Thomas Gleixner
2022-11-21 14:38 ` [patch V2 29/33] PCI/MSI: Provide pci_ims_alloc/free_irq() Thomas Gleixner
2022-11-24 3:11 ` Tian, Kevin
2022-11-21 14:38 ` [patch V2 30/33] x86/apic/msi: Enable PCI/IMS Thomas Gleixner
2022-11-21 14:38 ` [patch V2 31/33] iommu/vt-d: " Thomas Gleixner
2022-11-24 3:17 ` Tian, Kevin
2022-11-24 9:37 ` Thomas Gleixner
2022-11-24 13:14 ` Jason Gunthorpe
2022-11-24 13:21 ` Thomas Gleixner
2022-11-28 1:54 ` Tian, Kevin
2022-11-21 14:38 ` [patch V2 32/33] iommu/amd: " Thomas Gleixner
2022-11-21 14:38 ` [patch V2 33/33] irqchip: Add IDXD Interrupt Message Store driver Thomas Gleixner
2022-11-24 3:19 ` Tian, Kevin
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20221121091327.052582141@linutronix.de \
--to=tglx@linutronix.de \
--cc=alex.williamson@redhat.com \
--cc=allenbh@gmail.com \
--cc=ashok.raj@intel.com \
--cc=bhelgaas@google.com \
--cc=dan.j.williams@intel.com \
--cc=darwi@linutronix.de \
--cc=dave.jiang@intel.com \
--cc=gregkh@linuxfoundation.org \
--cc=jdmason@kudzu.us \
--cc=jgg@mellanox.com \
--cc=joro@8bytes.org \
--cc=kevin.tian@intel.com \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-pci@vger.kernel.org \
--cc=logang@deltatee.com \
--cc=lorenzo.pieralisi@arm.com \
--cc=maz@kernel.org \
--cc=will@kernel.org \
--cc=x86@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).