linux-pci.vger.kernel.org archive mirror
 help / color / mirror / Atom feed
From: Thomas Gleixner <tglx@linutronix.de>
To: LKML <linux-kernel@vger.kernel.org>
Cc: x86@kernel.org, Joerg Roedel <joro@8bytes.org>,
	Will Deacon <will@kernel.org>,
	linux-pci@vger.kernel.org, Bjorn Helgaas <bhelgaas@google.com>,
	Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
	Marc Zyngier <maz@kernel.org>,
	Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
	Jason Gunthorpe <jgg@mellanox.com>,
	Dave Jiang <dave.jiang@intel.com>,
	Alex Williamson <alex.williamson@redhat.com>,
	Kevin Tian <kevin.tian@intel.com>,
	Dan Williams <dan.j.williams@intel.com>,
	Logan Gunthorpe <logang@deltatee.com>,
	Ashok Raj <ashok.raj@intel.com>, Jon Mason <jdmason@kudzu.us>,
	Allen Hubbe <allenbh@gmail.com>
Subject: [patch V2 19/33] genirq/msi: Provide msi_desc::msi_data
Date: Mon, 21 Nov 2022 15:38:09 +0100 (CET)	[thread overview]
Message-ID: <20221121091327.546352933@linutronix.de> (raw)
In-Reply-To: 20221121083657.157152924@linutronix.de

The upcoming support for PCI/IMS requires to store some information related
to the message handling in the MSI descriptor, e.g. PASID or a pointer to a
queue.

Provide a generic storage struct which maps over the existing PCI specific
storage which means the size of struct msi_desc is not getting bigger.

It contains a iomem pointer for device memory based IMS and a union of a
u64 and a void pointer which allows the device specific IMS implementations
to store the necessary information.

The iomem pointer is set up by the domain allocation functions.

The data union msi_dev_cookie is going to be handed in when allocating an
interrupt on an IMS domain so the irq chip callbacks of the IMS domain have
the necessary per vector information available. It also comes in handy when
cleaning up the platform MSI code for wire to MSI bridges which need to
hand down the type information to the underlying interrupt domain.

For the core code the cookie is opaque and meaningless. It just stores it
during an allocation through the upcoming interfaces for IMS and wire to
MSI brigdes.

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
---
 include/linux/msi.h     |   38 +++++++++++++++++++++++++++++++++++++-
 include/linux/msi_api.h |   17 +++++++++++++++++
 2 files changed, 54 insertions(+), 1 deletion(-)

--- a/include/linux/msi.h
+++ b/include/linux/msi.h
@@ -125,6 +125,38 @@ struct pci_msi_desc {
 	};
 };
 
+/**
+ * union msi_domain_cookie - Opaque MSI domain specific data
+ * @value:	u64 value store
+ * @ptr:	Pointer to domain specific data
+ * @iobase:	Domain specific IOmem pointer
+ *
+ * The content of this data is implementation defined and used by the MSI
+ * domain to store domain specific information which is requried for
+ * interrupt chip callbacks.
+ */
+union msi_domain_cookie {
+	u64	value;
+	void	*ptr;
+	void	__iomem *iobase;
+};
+
+/**
+ * struct msi_desc_data - Generic MSI descriptor data
+ * @dcookie:	Cookie for MSI domain specific data which is required
+ *		for irq_chip callbacks
+ * @icookie:	Cookie for the MSI interrupt instance provided by
+ *		the usage site to the allocation function
+ *
+ * The content of this data is implementation defined, e.g. PCI/IMS
+ * implementations define the meaning of the data. The MSI core ignores
+ * this data completely.
+ */
+struct msi_desc_data {
+	union msi_domain_cookie		dcookie;
+	union msi_instance_cookie	icookie;
+};
+
 #define MSI_MAX_INDEX		((unsigned int)USHRT_MAX)
 
 /**
@@ -142,6 +174,7 @@ struct pci_msi_desc {
  *
  * @msi_index:	Index of the msi descriptor
  * @pci:	PCI specific msi descriptor data
+ * @data:	Generic MSI descriptor data
  */
 struct msi_desc {
 	/* Shared device/bus type independent data */
@@ -161,7 +194,10 @@ struct msi_desc {
 	void *write_msi_msg_data;
 
 	u16				msi_index;
-	struct pci_msi_desc		pci;
+	union {
+		struct pci_msi_desc	pci;
+		struct msi_desc_data	data;
+	};
 };
 
 /*
--- a/include/linux/msi_api.h
+++ b/include/linux/msi_api.h
@@ -19,6 +19,23 @@ enum msi_domain_ids {
 };
 
 /**
+ * union msi_instance_cookie - MSI instance cookie
+ * @value:	u64 value store
+ * @ptr:	Pointer to usage site specific data
+ *
+ * This cookie is handed to the IMS allocation function and stored in the
+ * MSI descriptor for the interrupt chip callbacks.
+ *
+ * The content of this cookie is MSI domain implementation defined.  For
+ * PCI/IMS implementations this could be a PASID or a pointer to queue
+ * memory.
+ */
+union msi_instance_cookie {
+	u64	value;
+	void	*ptr;
+};
+
+/**
  * msi_map - Mapping between MSI index and Linux interrupt number
  * @index:	The MSI index, e.g. slot in the MSI-X table or
  *		a software managed index if >= 0. If negative


  parent reply	other threads:[~2022-11-21 14:39 UTC|newest]

Thread overview: 71+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-11-21 14:37 [patch V2 00/33] genirq, PCI/MSI: Support for per device MSI and PCI/IMS - Part 3 implementation Thomas Gleixner
2022-11-21 14:37 ` [patch V2 01/33] genirq/msi: Rearrange MSI domain flags Thomas Gleixner
2022-11-21 14:37 ` [patch V2 02/33] genirq/msi: Provide struct msi_parent_ops Thomas Gleixner
2022-11-23  7:57   ` Tian, Kevin
2022-11-23 11:28     ` Thomas Gleixner
2022-11-24  0:53       ` Tian, Kevin
2022-11-21 14:37 ` [patch V2 03/33] genirq/msi: Provide data structs for per device domains Thomas Gleixner
2022-11-23  7:57   ` Tian, Kevin
2022-11-23 11:29     ` Thomas Gleixner
2022-11-21 14:37 ` [patch V2 04/33] genirq/msi: Add size info to struct msi_domain_info Thomas Gleixner
2022-11-21 14:37 ` [patch V2 05/33] genirq/msi: Split msi_create_irq_domain() Thomas Gleixner
2022-11-21 14:37 ` [patch V2 06/33] genirq/irqdomain: Add irq_domain::dev for per device MSI domains Thomas Gleixner
2022-11-21 14:37 ` [patch V2 07/33] genirq/msi: Provide msi_create/free_device_irq_domain() Thomas Gleixner
2022-11-23  8:02   ` Tian, Kevin
2022-11-23 11:38     ` Thomas Gleixner
2022-11-23 21:01       ` Thomas Gleixner
2022-11-24  1:07       ` Tian, Kevin
2022-11-24  8:36         ` Thomas Gleixner
2022-11-28  1:47           ` Tian, Kevin
2022-11-21 14:37 ` [patch V2 08/33] genirq/msi: Provide msi_match_device_domain() Thomas Gleixner
2022-11-21 14:37 ` [patch V2 09/33] genirq/msi: Add range checking to msi_insert_desc() Thomas Gleixner
2022-11-21 14:37 ` [patch V2 10/33] PCI/MSI: Split __pci_write_msi_msg() Thomas Gleixner
2022-11-21 14:37 ` [patch V2 11/33] genirq/msi: Provide BUS_DEVICE_PCI_MSI[X] Thomas Gleixner
2022-11-21 14:38 ` [patch V2 12/33] PCI/MSI: Add support for per device MSI[X] domains Thomas Gleixner
2022-11-23  8:08   ` Tian, Kevin
2022-11-23 11:41     ` Thomas Gleixner
2022-11-23 21:50       ` Thomas Gleixner
2022-11-24  1:08         ` Tian, Kevin
2022-11-21 14:38 ` [patch V2 13/33] x86/apic/vector: Provide MSI parent domain Thomas Gleixner
2022-11-23  8:16   ` Tian, Kevin
2022-11-23 13:42     ` Thomas Gleixner
2022-11-24  1:10       ` Tian, Kevin
2022-11-21 14:38 ` [patch V2 14/33] PCI/MSI: Remove unused pci_dev_has_special_msi_domain() Thomas Gleixner
2022-11-21 14:38 ` [patch V2 15/33] iommu/vt-d: Switch to MSI parent domains Thomas Gleixner
2022-11-21 14:38 ` [patch V2 16/33] iommu/amd: Switch to MSI base domains Thomas Gleixner
2022-11-21 14:38 ` [patch V2 17/33] x86/apic/msi: Remove arch_create_remap_msi_irq_domain() Thomas Gleixner
2022-11-21 14:38 ` [patch V2 18/33] genirq/msi: Provide struct msi_map Thomas Gleixner
2022-11-21 14:38 ` Thomas Gleixner [this message]
2022-11-23  8:27   ` [patch V2 19/33] genirq/msi: Provide msi_desc::msi_data Tian, Kevin
2022-11-23 11:41     ` Thomas Gleixner
2022-11-21 14:38 ` [patch V2 20/33] genirq/msi: Provide msi_domain_ops::prepare_desc() Thomas Gleixner
2022-11-21 14:38 ` [patch V2 21/33] genirq/msi: Provide msi_domain_alloc_irq_at() Thomas Gleixner
2022-11-24  2:54   ` Tian, Kevin
2022-11-21 14:38 ` [patch V2 22/33] genirq/msi: Provide MSI_FLAG_MSIX_ALLOC_DYN Thomas Gleixner
2022-11-21 14:38 ` [patch V2 23/33] PCI/MSI: Split MSI-X descriptor setup Thomas Gleixner
2022-11-21 14:38 ` [patch V2 24/33] PCI/MSI: Provide prepare_desc() MSI domain op Thomas Gleixner
2022-11-21 14:38 ` [patch V2 25/33] PCI/MSI: Provide post-enable dynamic allocation interfaces for MSI-X Thomas Gleixner
2022-11-24  2:58   ` Tian, Kevin
2022-11-24  9:08     ` Thomas Gleixner
2022-11-28  1:49       ` Tian, Kevin
2022-11-21 14:38 ` [patch V2 26/33] x86/apic/msi: Enable MSI_FLAG_PCI_MSIX_ALLOC_DYN Thomas Gleixner
2022-11-21 14:38 ` [patch V2 27/33] genirq/msi: Provide constants for PCI/IMS support Thomas Gleixner
2022-11-24  3:01   ` Tian, Kevin
2022-11-24  9:10     ` Thomas Gleixner
2022-11-24 13:09       ` Jason Gunthorpe
2022-11-24 13:28         ` Thomas Gleixner
2022-11-21 14:38 ` [patch V2 28/33] PCI/MSI: Provide IMS (Interrupt Message Store) support Thomas Gleixner
2022-11-24  3:10   ` Tian, Kevin
2022-11-24  9:10     ` Thomas Gleixner
2022-11-21 14:38 ` [patch V2 29/33] PCI/MSI: Provide pci_ims_alloc/free_irq() Thomas Gleixner
2022-11-24  3:11   ` Tian, Kevin
2022-11-21 14:38 ` [patch V2 30/33] x86/apic/msi: Enable PCI/IMS Thomas Gleixner
2022-11-21 14:38 ` [patch V2 31/33] iommu/vt-d: " Thomas Gleixner
2022-11-24  3:17   ` Tian, Kevin
2022-11-24  9:37     ` Thomas Gleixner
2022-11-24 13:14       ` Jason Gunthorpe
2022-11-24 13:21         ` Thomas Gleixner
2022-11-28  1:54           ` Tian, Kevin
2022-11-21 14:38 ` [patch V2 32/33] iommu/amd: " Thomas Gleixner
2022-11-21 14:38 ` [patch V2 33/33] irqchip: Add IDXD Interrupt Message Store driver Thomas Gleixner
2022-11-24  3:19   ` Tian, Kevin

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20221121091327.546352933@linutronix.de \
    --to=tglx@linutronix.de \
    --cc=alex.williamson@redhat.com \
    --cc=allenbh@gmail.com \
    --cc=ashok.raj@intel.com \
    --cc=bhelgaas@google.com \
    --cc=dan.j.williams@intel.com \
    --cc=dave.jiang@intel.com \
    --cc=gregkh@linuxfoundation.org \
    --cc=jdmason@kudzu.us \
    --cc=jgg@mellanox.com \
    --cc=joro@8bytes.org \
    --cc=kevin.tian@intel.com \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-pci@vger.kernel.org \
    --cc=logang@deltatee.com \
    --cc=lorenzo.pieralisi@arm.com \
    --cc=maz@kernel.org \
    --cc=will@kernel.org \
    --cc=x86@kernel.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).