From: Jonathan Cameron <Jonathan.Cameron@Huawei.com>
To: Dave Jiang <dave.jiang@intel.com>
Cc: <linux-cxl@vger.kernel.org>, <linux-pci@vger.kernel.org>,
<dan.j.williams@intel.com>, <ira.weiny@intel.com>,
<vishal.l.verma@intel.com>, <alison.schofield@intel.com>,
<rostedt@goodmis.org>, <terry.bowman@amd.com>,
<bhelgaas@google.com>
Subject: Re: [PATCH v3 10/11] PCI/AER: Add optional logging callback for correctable error
Date: Mon, 21 Nov 2022 12:17:20 +0000 [thread overview]
Message-ID: <20221121121720.0000541d@Huawei.com> (raw)
In-Reply-To: <20221121120527.0000608e@Huawei.com>
On Mon, 21 Nov 2022 12:05:27 +0000
Jonathan Cameron <Jonathan.Cameron@Huawei.com> wrote:
> On Fri, 18 Nov 2022 10:09:02 -0700
> Dave Jiang <dave.jiang@intel.com> wrote:
>
> > Some new devices such as CXL devices may want to record additional error
> > information on a corrected error. Add a callback to allow the PCI device
> > driver to do additional logging and/or error handling.
>
> Probably want to be a little careful about talking about error handling for
> corrected errors. It does make sense if you are doing stats based offlining
> of flaky parts of devices (we do this on some of our crypto and similar
> accelerators), but that isn't really 'error handling'.
Ah I'd also forgotten the mess of 'correctable' in PCIE (6.2.2.1 in PCIe r6.0 base)
Reality is that complex text means that the hardware can correct it without
intervention (though it may be other hardware, and it may not correct it, in which
case the source of the AER error should then issue an uncorrectable error message.)
Basic point stands but language is tricky around this.
Jonathan
>
> Agreed with other review that it might warrant some documentation but as
> said their, Bjorn's call to make!
>
> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
>
> >
> > Cc: Bjorn Helgaas <bhelgaas@google.com>
> > Suggested-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> > Signed-off-by: Dave Jiang <dave.jiang@intel.com>
> > ---
> > drivers/pci/pcie/aer.c | 8 +++++++-
> > include/linux/pci.h | 3 +++
> > 2 files changed, 10 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c
> > index e2d8a74f83c3..af1b5eecbb11 100644
> > --- a/drivers/pci/pcie/aer.c
> > +++ b/drivers/pci/pcie/aer.c
> > @@ -961,8 +961,14 @@ static void handle_error_source(struct pci_dev *dev, struct aer_err_info *info)
> > if (aer)
> > pci_write_config_dword(dev, aer + PCI_ERR_COR_STATUS,
> > info->status);
> > - if (pcie_aer_is_native(dev))
> > + if (pcie_aer_is_native(dev)) {
> > + struct pci_driver *pdrv = dev->driver;
> > +
> > + if (pdrv && pdrv->err_handler &&
> > + pdrv->err_handler->cor_error_log)
> > + pdrv->err_handler->cor_error_log(dev);
> > pcie_clear_device_status(dev);
> > + }
> > } else if (info->severity == AER_NONFATAL)
> > pcie_do_recovery(dev, pci_channel_io_normal, aer_root_reset);
> > else if (info->severity == AER_FATAL)
> > diff --git a/include/linux/pci.h b/include/linux/pci.h
> > index 575849a100a3..54939b3426a9 100644
> > --- a/include/linux/pci.h
> > +++ b/include/linux/pci.h
> > @@ -844,6 +844,9 @@ struct pci_error_handlers {
> >
> > /* Device driver may resume normal operations */
> > void (*resume)(struct pci_dev *dev);
> > +
> > + /* Allow device driver to record more details of a correctable error */
> > + void (*cor_error_log)(struct pci_dev *dev);
> > };
> >
> >
> >
> >
>
next prev parent reply other threads:[~2022-11-21 12:17 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-18 17:08 [PATCH v3 00/11] cxl/pci: Add fundamental error handling Dave Jiang
2022-11-18 17:08 ` [PATCH v3 01/11] cxl/pci: Cleanup repeated code in cxl_probe_regs() helpers Dave Jiang
2022-11-18 17:08 ` [PATCH v3 02/11] cxl/pci: Cleanup cxl_map_device_regs() Dave Jiang
2022-11-18 17:08 ` [PATCH v3 03/11] cxl/pci: Kill cxl_map_regs() Dave Jiang
2022-11-18 17:08 ` [PATCH v3 04/11] cxl/core/regs: Make cxl_map_{component, device}_regs() device generic Dave Jiang
2022-11-18 17:08 ` [PATCH v3 05/11] cxl/port: Limit the port driver to just the HDM Decoder Capability Dave Jiang
2022-11-18 17:08 ` [PATCH v3 06/11] cxl/pci: Prepare for mapping RAS Capability Structure Dave Jiang
2022-11-18 17:08 ` [PATCH v3 07/11] cxl/pci: Find and map the " Dave Jiang
2022-11-18 17:08 ` [PATCH v3 08/11] cxl/pci: add tracepoint events for CXL RAS Dave Jiang
2022-11-18 17:17 ` Steven Rostedt
2022-11-18 17:31 ` Dave Jiang
2022-11-21 11:37 ` Jonathan Cameron
2022-11-21 13:08 ` Shiju Jose
2022-11-28 17:54 ` Dave Jiang
2022-11-18 17:08 ` [PATCH v3 09/11] cxl/pci: Add (hopeful) error handling support Dave Jiang
2022-11-21 11:56 ` Jonathan Cameron
2022-11-18 17:09 ` [PATCH v3 10/11] PCI/AER: Add optional logging callback for correctable error Dave Jiang
2022-11-19 1:08 ` Sathyanarayanan Kuppuswamy
2022-11-28 18:19 ` Dave Jiang
2022-11-21 12:05 ` Jonathan Cameron
2022-11-21 12:17 ` Jonathan Cameron [this message]
2022-11-28 21:01 ` Dave Jiang
2022-11-18 17:09 ` [PATCH v3 11/11] cxl/pci: Add callback to log AER " Dave Jiang
2022-11-21 12:21 ` Jonathan Cameron
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