From: Thomas Gleixner <tglx@linutronix.de>
To: LKML <linux-kernel@vger.kernel.org>
Cc: Will Deacon <will@kernel.org>,
linux-pci@vger.kernel.org, Bjorn Helgaas <bhelgaas@google.com>,
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
Marc Zyngier <maz@kernel.org>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
Jason Gunthorpe <jgg@mellanox.com>, Andrew Lunn <andrew@lunn.ch>,
Gregory Clement <gregory.clement@bootlin.com>,
Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>,
Ammar Faizi <ammarfaizi2@gnuweeb.org>,
Robin Murphy <robin.murphy@arm.com>,
Lorenzo Pieralisi <lpieralisi@kernel.org>,
Nishanth Menon <nm@ti.com>, Tero Kristo <kristo@kernel.org>,
Santosh Shilimkar <ssantosh@kernel.org>,
linux-arm-kernel@lists.infradead.org,
Vinod Koul <vkoul@kernel.org>, Sinan Kaya <okaya@kernel.org>,
Andy Gross <agross@kernel.org>,
Bjorn Andersson <andersson@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
Shameerali Kolothum Thodi <shameerali.kolothum.thodi@huawei.com>,
Zenghui Yu <yuzenghui@huawei.com>,
Shawn Guo <shawnguo@kernel.org>,
Sascha Hauer <s.hauer@pengutronix.de>,
Fabio Estevam <festevam@gmail.com>
Subject: [patch V2 24/40] irqchip/mbigen: Prepare for real per device MSI
Date: Mon, 21 Nov 2022 15:39:58 +0100 (CET) [thread overview]
Message-ID: <20221121140049.807060253@linutronix.de> (raw)
In-Reply-To: 20221121135653.208611233@linutronix.de
The core infrastructure has everything in place to switch MBIGEN to per
device MSI domains and avoid the convoluted construct of the existing
platform-MSI layering violation.
The new infrastructure provides a wired interrupt specific interface in the
MSI core which converts the 'hardware interrupt number + trigger type'
allocation which is required for wired interrupts in the regular irqdomain
code to a normal MSI allocation.
The hardware interrupt number and the trigger type are stored in the MSI
descriptor device cookie by the core code so the MBIGEN specific code can
retrieve them.
The new per device domain is only instantiated when the irqdomain which is
associated to the MBIGEN device provides MSI parent functionality. Up to
that point it invokes the existing code. Once the parent is converted the
code for the current platform-MSI mechanism is removed.
The new domain shares the interrupt chip callbacks and the translation
function. The only new functionality aside of filling out the
msi_domain_template is a domain specific set_desc() callback, which will go
away once all platform-MSI code has been converted.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Marc Zyngier <maz@kernel.org>
Cc: Shameerali Kolothum Thodi <shameerali.kolothum.thodi@huawei.com>
Cc: Zenghui Yu <yuzenghui@huawei.com>
---
drivers/irqchip/irq-mbigen.c | 100 ++++++++++++++++++++++++++++++-------------
1 file changed, 71 insertions(+), 29 deletions(-)
--- a/drivers/irqchip/irq-mbigen.c
+++ b/drivers/irqchip/irq-mbigen.c
@@ -135,24 +135,14 @@ static int mbigen_set_type(struct irq_da
return 0;
}
-static struct irq_chip mbigen_irq_chip = {
- .name = "mbigen-v2",
- .irq_mask = irq_chip_mask_parent,
- .irq_unmask = irq_chip_unmask_parent,
- .irq_eoi = mbigen_eoi_irq,
- .irq_set_type = mbigen_set_type,
- .irq_set_affinity = irq_chip_set_affinity_parent,
-};
-
-static void mbigen_write_msg(struct msi_desc *desc, struct msi_msg *msg)
+static void mbigen_write_msi_msg(struct irq_data *d, struct msi_msg *msg)
{
- struct irq_data *d = irq_get_irq_data(desc->irq);
void __iomem *base = d->chip_data;
u32 val;
if (!msg->address_lo && !msg->address_hi)
return;
-
+
base += get_mbigen_vec_reg(d->hwirq);
val = readl_relaxed(base);
@@ -165,10 +155,8 @@ static void mbigen_write_msg(struct msi_
writel_relaxed(val, base);
}
-static int mbigen_domain_translate(struct irq_domain *d,
- struct irq_fwspec *fwspec,
- unsigned long *hwirq,
- unsigned int *type)
+static int mbigen_domain_translate(struct irq_domain *d, struct irq_fwspec *fwspec,
+ unsigned long *hwirq, unsigned int *type)
{
if (is_of_node(fwspec->fwnode) || is_acpi_device_node(fwspec->fwnode)) {
if (fwspec->param_count != 2)
@@ -192,6 +180,17 @@ static int mbigen_domain_translate(struc
return -EINVAL;
}
+/* The following section will go away once ITS provides a MSI parent */
+
+static struct irq_chip mbigen_irq_chip = {
+ .name = "mbigen-v2",
+ .irq_mask = irq_chip_mask_parent,
+ .irq_unmask = irq_chip_unmask_parent,
+ .irq_eoi = mbigen_eoi_irq,
+ .irq_set_type = mbigen_set_type,
+ .irq_set_affinity = irq_chip_set_affinity_parent,
+};
+
static int mbigen_irq_domain_alloc(struct irq_domain *domain,
unsigned int virq,
unsigned int nr_irqs,
@@ -232,13 +231,65 @@ static const struct irq_domain_ops mbige
.free = mbigen_irq_domain_free,
};
+static void mbigen_write_msg(struct msi_desc *desc, struct msi_msg *msg)
+{
+ mbigen_write_msi_msg(irq_get_irq_data(desc->irq), msg);
+}
+
+/* End of to be removed section */
+
+static void mbigen_domain_set_desc(msi_alloc_info_t *arg, struct msi_desc *desc)
+{
+ arg->desc = desc;
+ arg->hwirq = (u32)desc->data.icookie.value;
+}
+
+static const struct msi_domain_template mbigen_msi_template = {
+ .chip = {
+ .name = "mbigen-v2",
+ .irq_mask = irq_chip_mask_parent,
+ .irq_unmask = irq_chip_unmask_parent,
+ .irq_eoi = mbigen_eoi_irq,
+ .irq_set_type = mbigen_set_type,
+ .irq_write_msi_msg = mbigen_write_msi_msg,
+ },
+
+ .ops = {
+ .set_desc = mbigen_domain_set_desc,
+ .msi_translate = mbigen_domain_translate,
+ },
+
+ .info = {
+ .bus_token = DOMAIN_BUS_WIRED_TO_MSI,
+ .flags = MSI_FLAG_USE_DEV_FWNODE,
+ },
+};
+
+static bool mbigen_create_device_domain(struct device *dev, unsigned int size,
+ struct mbigen_device *mgn_chip)
+{
+ struct irq_domain *domain = dev->msi.domain;
+
+ if (WARN_ON_ONCE(!domain))
+ return false;
+
+ if (irq_domain_is_msi_parent(domain)) {
+ return msi_create_device_irq_domain(dev, MSI_DEFAULT_DOMAIN,
+ &mbigen_msi_template, size,
+ NULL, mgn_chip->base);
+ }
+
+ /* Remove once ITS provides MSI parent */
+ return !!platform_msi_create_device_domain(dev, size, mbigen_write_msg,
+ &mbigen_domain_ops, mgn_chip);
+}
+
static int mbigen_of_create_domain(struct platform_device *pdev,
struct mbigen_device *mgn_chip)
{
- struct device *parent;
struct platform_device *child;
- struct irq_domain *domain;
struct device_node *np;
+ struct device *parent;
u32 num_pins;
for_each_child_of_node(pdev->dev.of_node, np) {
@@ -259,11 +310,7 @@ static int mbigen_of_create_domain(struc
return -EINVAL;
}
- domain = platform_msi_create_device_domain(&child->dev, num_pins,
- mbigen_write_msg,
- &mbigen_domain_ops,
- mgn_chip);
- if (!domain) {
+ if (!mbigen_create_device_domain(&child->dev, num_pins, mgn_chip)) {
of_node_put(np);
return -ENOMEM;
}
@@ -282,7 +329,6 @@ MODULE_DEVICE_TABLE(acpi, mbigen_acpi_ma
static int mbigen_acpi_create_domain(struct platform_device *pdev,
struct mbigen_device *mgn_chip)
{
- struct irq_domain *domain;
u32 num_pins = 0;
int ret;
@@ -313,11 +359,7 @@ static int mbigen_acpi_create_domain(str
if (ret || num_pins == 0)
return -EINVAL;
- domain = platform_msi_create_device_domain(&pdev->dev, num_pins,
- mbigen_write_msg,
- &mbigen_domain_ops,
- mgn_chip);
- if (!domain)
+ if (!mbigen_create_device_domain(&pdev->dev, num_pins, mgn_chip))
return -ENOMEM;
return 0;
next prev parent reply other threads:[~2022-11-21 14:50 UTC|newest]
Thread overview: 57+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-21 14:39 [patch V2 00/40] genirq, irqchip: Convert ARM MSI handling to per device MSI domains Thomas Gleixner
2022-11-21 14:39 ` [patch V2 01/40] irqchip/irq-mvebu-icu: Fix works by chance pointer assignment Thomas Gleixner
2022-11-24 12:50 ` Marc Zyngier
2022-11-21 14:39 ` [patch V2 02/40] ACPI/IORT: Make prototype of iort_pmsi_get_dev_id() always available Thomas Gleixner
2022-11-21 15:13 ` Robin Murphy
2022-11-21 14:39 ` [patch V2 03/40] irqchip/gic-v2m: Include arm-gic-common.h Thomas Gleixner
2022-11-24 12:51 ` Marc Zyngier
2022-11-21 14:39 ` [patch V2 04/40] irqchip/gic-v2m: Mark a few functions __init Thomas Gleixner
2022-11-24 12:54 ` Marc Zyngier
2022-11-21 14:39 ` [patch V2 05/40] irqchip/ti-sci-inta: Fix kernel doc Thomas Gleixner
2022-11-24 12:54 ` Marc Zyngier
2022-11-21 14:39 ` [patch V2 06/40] PCI/MSI: Provide static key for parent mask/unmask Thomas Gleixner
2022-11-24 13:04 ` Marc Zyngier
2022-11-24 13:17 ` Thomas Gleixner
2022-11-24 13:38 ` Marc Zyngier
2022-11-25 0:11 ` Thomas Gleixner
2023-05-22 14:19 ` Thomas Gleixner
2023-05-23 10:25 ` Marc Zyngier
2023-05-23 13:05 ` Thomas Gleixner
2023-05-31 8:35 ` Marc Zyngier
2022-11-21 14:39 ` [patch V2 07/40] irqchip/gic-v3: Make gic_irq_domain_select() robust for zero parameter count Thomas Gleixner
2022-11-21 14:39 ` [patch V2 08/40] genirq/irqdomain: Remove the param count restriction from select() Thomas Gleixner
2022-11-21 14:39 ` [patch V2 09/40] genirq/msi: Extend msi_parent_ops Thomas Gleixner
2022-11-21 14:39 ` [patch V2 10/40] irqchip: Provide irq-gic-lib Thomas Gleixner
2022-11-21 14:39 ` [patch V2 11/40] irqchip/gic-v3-its: Provide MSI parent infrastructure Thomas Gleixner
2022-11-21 14:39 ` [patch V2 12/40] irqchip/gic-msi-lib: Prepare for PCI MSI/MSIX Thomas Gleixner
2022-11-21 14:39 ` [patch V2 13/40] irqchip/gic-v3-its: Provide MSI parent for PCI/MSI[-X] Thomas Gleixner
2022-11-21 14:39 ` [patch V2 14/40] genirq/irqdomain: Add BUS_DOMAIN_DEVICE_MSI Thomas Gleixner
2022-11-21 14:39 ` [patch V2 15/40] irqchip/gic-msi-lib: Prepare for DEVICE MSI to replace platform MSI Thomas Gleixner
2022-11-21 14:39 ` [patch V2 16/40] platform-msi: Prepare for real per device domains Thomas Gleixner
2022-11-21 14:39 ` [patch V2 17/40] irqchip: Convert all platform MSI users to the new API Thomas Gleixner
2022-11-21 14:39 ` [patch V2 18/40] genirq/msi: Provide optional translation op Thomas Gleixner
2022-11-21 14:39 ` [patch V2 19/40] genirq/msi: Split msi_domain_alloc_irq_at() Thomas Gleixner
2022-11-21 14:39 ` [patch V2 20/40] genirq/msi: Provide BUS DEVICE_MSI_WIRED Thomas Gleixner
2022-11-21 14:39 ` [patch V2 21/40] genirq/msi: Optionally use dev->fwnode for device domain Thomas Gleixner
2022-11-21 14:39 ` [patch V2 22/40] genirq/msi: Provide allocation/free functions for "wired" MSI interrupts Thomas Gleixner
2022-11-21 14:39 ` [patch V2 23/40] genirq/irqdomain: Reroute device MSI create_mapping Thomas Gleixner
2022-11-21 14:39 ` Thomas Gleixner [this message]
2022-11-21 14:39 ` [patch V2 25/40] irqchip/gic-msi-lib: Prepare for DOMAIN_BUS_WIRED_TO_MSI Thomas Gleixner
2022-11-21 14:40 ` [patch V2 26/40] irqchip/gic-v3-its: Switch platform MSI to MSI parent Thomas Gleixner
2022-11-21 14:40 ` [patch V2 27/40] irqchip/mbigen: Remove platform_msi_create_device_domain() fallback Thomas Gleixner
2022-11-21 14:40 ` [patch V2 28/40] genirq/msi: Remove platform_msi_create_device_domain() Thomas Gleixner
2022-11-21 14:40 ` [patch V2 29/40] genirq/gic-v3-mbi: Remove unused wired MSI mechanics Thomas Gleixner
2022-11-21 14:40 ` [patch V2 30/40] genirq/gic-v3-mbi: Switch to MSI parent Thomas Gleixner
2022-11-21 14:40 ` [patch V2 31/40] irqchip/gic-v2m: Switch to device MSI Thomas Gleixner
2022-11-21 14:40 ` [patch V2 32/40] genirq/msi: Provide MSI_FLAG_PARENT_PM_DEV Thomas Gleixner
2022-11-21 14:40 ` [patch V2 33/40] irqchip/imx-mu-msi: Switch to MSI parent Thomas Gleixner
2022-11-28 20:47 ` Frank Li
2022-11-28 21:03 ` Thomas Gleixner
2022-11-21 14:40 ` [patch V2 34/40] irqchip/irq-mvebu-icu: Prepare for real per device MSI Thomas Gleixner
2022-11-21 14:40 ` [patch V2 35/40] irqchip/mvebu-gicp: Switch to MSI parent Thomas Gleixner
2022-11-21 14:40 ` [patch V2 36/40] irqchip/mvebu-odmi: Switch to parent MSI Thomas Gleixner
2022-11-21 14:40 ` [patch V2 37/40] irqchip/irq-mvebu-sei: Switch to MSI parent Thomas Gleixner
2022-11-21 14:40 ` [patch V2 38/40] irqchip/irq-mvebu-icu: Remove platform MSI leftovers Thomas Gleixner
2022-11-21 14:40 ` [patch V2 39/40] genirq/msi: " Thomas Gleixner
2022-11-21 14:40 ` [patch V2 40/40] genirq/msi: Move msi_device_data to core Thomas Gleixner
2023-01-11 19:29 ` [patch V2 00/40] genirq, irqchip: Convert ARM MSI handling to per device MSI domains Frank Li
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