Re: PCI resource allocation mismatch with BIOS

[Lukas Wunner <lukas@wunner.de>]

On Tue, Nov 29, 2022 at 09:12:49AM -0700, Alex Williamson wrote:
> On Tue, 29 Nov 2022 17:06:26 +0100 Lukas Wunner <lukas@wunner.de> wrote:
> > On Tue, Nov 29, 2022 at 08:46:46AM -0700, Alex Williamson wrote:
> > > Maybe the elephant in the room is why it's apparently such common
> > > practice to need to perform a hard reset these devices outside of
> > > virtualization scenarios...  
> > 
> > These GPUs are used as accelerators in cloud environments.
> > 
> > They're reset to a pristine state when handed out to another tenant
> > to avoid info leaks from the previous tenant.
> > 
> > That should be a legitimate usage of PCIe reset, no?
> 
> Absolutely, but why the whole switch?  Thanks,

The reset is propagated down the hierarchy, so by resetting the
Switch Upstream Port, it is guaranteed that all endpoints are
reset with just a single operation.  Per PCIe r6.0.1 sec 6.6.1:

   "For a Switch, the following must cause a hot reset to be sent
    on all Downstream Ports:
    [...]
    Receiving a hot reset on the Upstream Port"

Thanks,

Lukas