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From: ira.weiny@intel.com
To: Dan Williams <dan.j.williams@intel.com>
Cc: Ira Weiny <ira.weiny@intel.com>,
	Jonathan Cameron <Jonathan.Cameron@huawei.com>,
	Bjorn Helgaas <bhelgaas@google.com>,
	Alison Schofield <alison.schofield@intel.com>,
	Vishal Verma <vishal.l.verma@intel.com>,
	Davidlohr Bueso <dave@stgolabs.net>,
	Dave Jiang <dave.jiang@intel.com>,
	linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org,
	linux-acpi@vger.kernel.org, linux-cxl@vger.kernel.org
Subject: [PATCH V4 9/9] cxl/test: Simulate event log overflow
Date: Sun, 11 Dec 2022 23:06:27 -0800	[thread overview]
Message-ID: <20221212070627.1372402-10-ira.weiny@intel.com> (raw)
In-Reply-To: <20221212070627.1372402-1-ira.weiny@intel.com>

From: Ira Weiny <ira.weiny@intel.com>

Log overflow is marked by a separate trace message.

Simulate a log with lots of messages and flag overflow until space is
cleared.

Reviewed-by: Dan Williams <dan.j.williams@intel.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Ira Weiny <ira.weiny@intel.com>

---
Changes from V3:
	Dan
		Move code to mem.c
---
 tools/testing/cxl/test/mem.c | 50 +++++++++++++++++++++++++++++++++++-
 1 file changed, 49 insertions(+), 1 deletion(-)

diff --git a/tools/testing/cxl/test/mem.c b/tools/testing/cxl/test/mem.c
index 73db722a8879..b2327a8de4a6 100644
--- a/tools/testing/cxl/test/mem.c
+++ b/tools/testing/cxl/test/mem.c
@@ -78,6 +78,8 @@ struct mock_event_log {
 	u16 clear_idx;
 	u16 cur_idx;
 	u16 nr_events;
+	u16 nr_overflow;
+	u16 overflow_reset;
 	struct cxl_event_record_raw *events[CXL_TEST_EVENT_CNT_MAX];
 };
 
@@ -116,6 +118,7 @@ static void event_reset_log(struct mock_event_log *log)
 {
 	log->cur_idx = 0;
 	log->clear_idx = 0;
+	log->nr_overflow = log->overflow_reset;
 }
 
 /* Handle can never be 0 use 1 based indexing for handle */
@@ -147,8 +150,12 @@ static void mes_add_event(struct mock_event_store *mes,
 		return;
 
 	log = &mes->mock_logs[log_type];
-	if (WARN_ON(log->nr_events >= CXL_TEST_EVENT_CNT_MAX))
+
+	if ((log->nr_events + 1) > CXL_TEST_EVENT_CNT_MAX) {
+		log->nr_overflow++;
+		log->overflow_reset = log->nr_overflow;
 		return;
+	}
 
 	log->events[log->nr_events] = event;
 	log->nr_events++;
@@ -159,6 +166,7 @@ static int mock_get_event(struct cxl_dev_state *cxlds,
 {
 	struct cxl_get_event_payload *pl;
 	struct mock_event_log *log;
+	u16 nr_overflow;
 	u8 log_type;
 	int i;
 
@@ -191,6 +199,19 @@ static int mock_get_event(struct cxl_dev_state *cxlds,
 	if (!event_log_empty(log))
 		pl->flags |= CXL_GET_EVENT_FLAG_MORE_RECORDS;
 
+	if (log->nr_overflow) {
+		u64 ns;
+
+		pl->flags |= CXL_GET_EVENT_FLAG_OVERFLOW;
+		pl->overflow_err_count = cpu_to_le16(nr_overflow);
+		ns = ktime_get_real_ns();
+		ns -= 5000000000; /* 5s ago */
+		pl->first_overflow_timestamp = cpu_to_le64(ns);
+		ns = ktime_get_real_ns();
+		ns -= 1000000000; /* 1s ago */
+		pl->last_overflow_timestamp = cpu_to_le64(ns);
+	}
+
 	return 0;
 }
 
@@ -231,6 +252,9 @@ static int mock_clear_event(struct cxl_dev_state *cxlds,
 		}
 	}
 
+	if (log->nr_overflow)
+		log->nr_overflow = 0;
+
 	/* Clear events */
 	log->clear_idx += pl->nr_recs;
 	return 0;
@@ -353,6 +377,30 @@ static void cxl_mock_add_event_logs(struct mock_event_store *mes)
 		      (struct cxl_event_record_raw *)&mem_module);
 	mes->ev_status |= CXLDEV_EVENT_STATUS_INFO;
 
+	mes_add_event(mes, CXL_EVENT_TYPE_FAIL, &maint_needed);
+	mes_add_event(mes, CXL_EVENT_TYPE_FAIL, &hardware_replace);
+	mes_add_event(mes, CXL_EVENT_TYPE_FAIL,
+		      (struct cxl_event_record_raw *)&dram);
+	mes_add_event(mes, CXL_EVENT_TYPE_FAIL,
+		      (struct cxl_event_record_raw *)&gen_media);
+	mes_add_event(mes, CXL_EVENT_TYPE_FAIL,
+		      (struct cxl_event_record_raw *)&mem_module);
+	mes_add_event(mes, CXL_EVENT_TYPE_FAIL, &hardware_replace);
+	mes_add_event(mes, CXL_EVENT_TYPE_FAIL,
+		      (struct cxl_event_record_raw *)&dram);
+	/* Overflow this log */
+	mes_add_event(mes, CXL_EVENT_TYPE_FAIL, &hardware_replace);
+	mes_add_event(mes, CXL_EVENT_TYPE_FAIL, &hardware_replace);
+	mes_add_event(mes, CXL_EVENT_TYPE_FAIL, &hardware_replace);
+	mes_add_event(mes, CXL_EVENT_TYPE_FAIL, &hardware_replace);
+	mes_add_event(mes, CXL_EVENT_TYPE_FAIL, &hardware_replace);
+	mes_add_event(mes, CXL_EVENT_TYPE_FAIL, &hardware_replace);
+	mes_add_event(mes, CXL_EVENT_TYPE_FAIL, &hardware_replace);
+	mes_add_event(mes, CXL_EVENT_TYPE_FAIL, &hardware_replace);
+	mes_add_event(mes, CXL_EVENT_TYPE_FAIL, &hardware_replace);
+	mes_add_event(mes, CXL_EVENT_TYPE_FAIL, &hardware_replace);
+	mes->ev_status |= CXLDEV_EVENT_STATUS_FAIL;
+
 	mes_add_event(mes, CXL_EVENT_TYPE_FATAL, &hardware_replace);
 	mes_add_event(mes, CXL_EVENT_TYPE_FATAL,
 		      (struct cxl_event_record_raw *)&dram);
-- 
2.37.2


  parent reply	other threads:[~2022-12-12  7:07 UTC|newest]

Thread overview: 36+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-12-12  7:06 [PATCH V4 0/9] CXL: Process event logs ira.weiny
2022-12-12  7:06 ` [PATCH V4 1/9] PCI/CXL: Export native CXL error reporting control ira.weiny
2022-12-13 19:12   ` Dan Williams
2022-12-16 14:09   ` Jonathan Cameron
2023-01-05  3:16   ` Ira Weiny
2023-01-05 16:56   ` Bjorn Helgaas
2022-12-12  7:06 ` [PATCH V4 2/9] cxl/mem: Read, trace, and clear events on driver load ira.weiny
2022-12-13  6:49   ` johnny
2022-12-13 18:56     ` Ira Weiny
2022-12-16 15:39   ` Jonathan Cameron
2022-12-16 21:54     ` Ira Weiny
2022-12-17 16:38       ` Jonathan Cameron
2022-12-18  0:21         ` Ira Weiny
2022-12-18 15:52           ` Jonathan Cameron
2022-12-18  0:25       ` johnny
2022-12-18 15:55         ` Jonathan Cameron
2023-01-04 23:53           ` Ira Weiny
2022-12-12  7:06 ` [PATCH V4 3/9] cxl/mem: Wire up event interrupts ira.weiny
2022-12-13 20:15   ` Dan Williams
2022-12-16 14:24   ` Jonathan Cameron
2022-12-16 18:42     ` Jonathan Cameron
2022-12-16 21:28       ` Ira Weiny
2022-12-17 16:40         ` Jonathan Cameron
2022-12-16 18:21   ` Jonathan Cameron
2022-12-16 21:33     ` Ira Weiny
2022-12-17 16:43       ` Jonathan Cameron
2022-12-12  7:06 ` [PATCH V4 4/9] cxl/mem: Trace General Media Event Record ira.weiny
2022-12-12  7:06 ` [PATCH V4 5/9] cxl/mem: Trace DRAM " ira.weiny
2022-12-12  7:06 ` [PATCH V4 6/9] cxl/mem: Trace Memory Module " ira.weiny
2022-12-12  7:06 ` [PATCH V4 7/9] cxl/test: Add generic mock events ira.weiny
2022-12-12  7:06 ` [PATCH V4 8/9] cxl/test: Add specific events ira.weiny
2022-12-12  7:06 ` ira.weiny [this message]
2022-12-16 12:25 ` [PATCH V4 0/9] CXL: Process event logs Jonathan Cameron
2022-12-16 17:01   ` Dan Williams
2022-12-16 18:15     ` Ira Weiny
2022-12-16 18:39     ` Jonathan Cameron

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