From: Jonathan Cameron <Jonathan.Cameron@Huawei.com>
To: <ira.weiny@intel.com>
Cc: Dan Williams <dan.j.williams@intel.com>,
Bjorn Helgaas <bhelgaas@google.com>,
Alison Schofield <alison.schofield@intel.com>,
Vishal Verma <vishal.l.verma@intel.com>,
Davidlohr Bueso <dave@stgolabs.net>,
Dave Jiang <dave.jiang@intel.com>,
Ben Widawsky <bwidawsk@kernel.org>,
Steven Rostedt <rostedt@goodmis.org>,
<linux-kernel@vger.kernel.org>, <linux-pci@vger.kernel.org>,
<linux-acpi@vger.kernel.org>, <linux-cxl@vger.kernel.org>,
Bjorn Helgaas <helgaas@kernel.org>
Subject: Re: [PATCH v6 2/8] cxl/mem: Wire up event interrupts
Date: Fri, 13 Jan 2023 12:28:45 +0000 [thread overview]
Message-ID: <20230113122845.00006be6@Huawei.com> (raw)
In-Reply-To: <20221216-cxl-ev-log-v6-2-346583105b30@intel.com>
On Mon, 09 Jan 2023 11:42:21 -0800
ira.weiny@intel.com wrote:
> From: Davidlohr Bueso <dave@stgolabs.net>
>
> Currently the only CXL features targeted for irq support require their
> message numbers to be within the first 16 entries. The device may
> however support less than 16 entries depending on the support it
> provides.
>
> Attempt to allocate these 16 irq vectors. If the device supports less
> then the PCI infrastructure will allocate that number. Upon successful
> allocation, users can plug in their respective isr at any point
> thereafter.
>
> CXL device events are signaled via interrupts. Each event log may have
> a different interrupt message number. These message numbers are
> reported in the Get Event Interrupt Policy mailbox command.
>
> Add interrupt support for event logs. Interrupts are allocated as
> shared interrupts. Therefore, all or some event logs can share the same
> message number.
>
> In addition all logs are queried on any interrupt in order of the most
> to least severe based on the status register.
>
> Finally place all event configuration logic into cxl_event_config().
> Previously the logic was a simple 'read all' on start up. But
> interrupts must be configured prior to any reads to ensure no events are
> missed. A single event configuration function results in a cleaner over
> all implementation.
>
> Cc: Bjorn Helgaas <helgaas@kernel.org>
> Cc: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> Co-developed-by: Ira Weiny <ira.weiny@intel.com>
> Signed-off-by: Ira Weiny <ira.weiny@intel.com>
> Signed-off-by: Davidlohr Bueso <dave@stgolabs.net>
>
> ---
> Changes from V5:
> Dan
> Addressed missed comments on V4
> https://lore.kernel.org/all/6398dd6ed80fa_b05d1294fc@dwillia2-xfh.jf.intel.com.notmuch/
You also added pci_set_master() :)
Which means I can now give
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
I only noticed because I couldn't remember why I'd not given a tag to v4.
Jonathan
next prev parent reply other threads:[~2023-01-13 12:29 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-01-09 19:42 [PATCH v6 0/8] cxl: Process event logs Ira Weiny
2023-01-09 19:42 ` [PATCH v6 1/8] cxl/mem: Read, trace, and clear events on driver load Ira Weiny
2023-01-13 12:22 ` Jonathan Cameron
2023-01-18 1:03 ` Ira Weiny
2023-01-09 19:42 ` [PATCH v6 2/8] cxl/mem: Wire up event interrupts ira.weiny
2023-01-13 12:28 ` Jonathan Cameron [this message]
2023-01-13 21:45 ` Ira Weiny
2023-01-09 19:42 ` [PATCH v6 3/8] cxl/mem: Trace General Media Event Record Ira Weiny
2023-01-13 12:34 ` Jonathan Cameron
2023-01-13 17:16 ` Davidlohr Bueso
2023-01-09 19:42 ` [PATCH v6 4/8] cxl/mem: Trace DRAM " Ira Weiny
2023-01-13 12:36 ` Jonathan Cameron
2023-01-13 19:09 ` Davidlohr Bueso
2023-01-09 19:42 ` [PATCH v6 5/8] cxl/mem: Trace Memory Module " Ira Weiny
2023-01-13 12:41 ` Jonathan Cameron
2023-01-18 1:12 ` Ira Weiny
2023-01-09 19:42 ` [PATCH v6 6/8] cxl/test: Add generic mock events Ira Weiny
2023-01-13 13:27 ` Jonathan Cameron
2023-01-09 19:42 ` [PATCH v6 7/8] cxl/test: Add specific events Ira Weiny
2023-01-09 19:42 ` [PATCH v6 8/8] cxl/test: Simulate event log overflow Ira Weiny
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