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From: Jonathan Cameron <Jonathan.Cameron@Huawei.com>
To: Greg KH <gregkh@linuxfoundation.org>
Cc: Leon Romanovsky <leon@kernel.org>,
	Alexander Shishkin <alexander.shishkin@linux.intel.com>,
	Bjorn Helgaas <bhelgaas@google.com>,
	Thomas Gleixner <tglx@linutronix.de>, <linux-pci@vger.kernel.org>,
	<linux-kernel@vger.kernel.org>, Marc Zyngier <maz@kernel.org>,
	<darwi@linutronix.de>, <elena.reshetova@intel.com>,
	<kirill.shutemov@linux.intel.com>,
	Mika Westerberg <mika.westerberg@linux.intel.com>,
	<stable@vger.kernel.org>, Lukas Wunner <lukas@wunner.de>
Subject: Re: [PATCH 1/2] PCI/MSI: Cache the MSIX table size
Date: Mon, 23 Jan 2023 10:22:37 +0000	[thread overview]
Message-ID: <20230123102237.00006bfa@Huawei.com> (raw)
In-Reply-To: <Y80WtujnO7kfduAZ@kroah.com>

On Sun, 22 Jan 2023 11:57:58 +0100
Greg KH <gregkh@linuxfoundation.org> wrote:

> On Sun, Jan 22, 2023 at 11:00:04AM +0200, Leon Romanovsky wrote:
> > On Thu, Jan 19, 2023 at 07:06:32PM +0200, Alexander Shishkin wrote:  
> > > A malicious device can change its MSIX table size between the table
> > > ioremap() and subsequent accesses, resulting in a kernel page fault in
> > > pci_write_msg_msix().
> > > 
> > > To avoid this, cache the table size observed at the moment of table
> > > ioremap() and use the cached value. This, however, does not help drivers
> > > that peek at the PCIE_MSIX_FLAGS register directly.
> > > 
> > > Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
> > > Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
> > > Cc: stable@vger.kernel.org
> > > ---
> > >  drivers/pci/msi/api.c | 7 ++++++-
> > >  drivers/pci/msi/msi.c | 2 +-
> > >  include/linux/pci.h   | 1 +
> > >  3 files changed, 8 insertions(+), 2 deletions(-)  
> > 
> > I'm not security expert here, but not sure that this protects from anything.
> > 1. Kernel relies on working and not-malicious HW. There are gazillion ways
> > to cause crashes other than changing MSI-X.  
> 
> Linux does NOT protect from malicious PCIe devices at this point in
> time, you are correct.  If we wish to change that model, then we can
> work on that with the explict understanding that most all drivers will
> need to change as will the bus logic for the busses involved.
> 
> To do piece-meal patches like this for no good reason is not a good idea
> as it achieves nothing in the end :(
> 
> thanks,
> 
> greg k-h

If you care enough about potential malicious PCIe devices, do device
attestation and reject any devices that don't support it (which means
rejecting pretty much everything today ;).
Or potentially limit what non attested devices are allowed to do.

+CC Lukas who is working on this.

Jonathan

  reply	other threads:[~2023-01-23 10:22 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-01-19 17:06 [PATCH 0/2] PCI/MSI: Hardening fixes Alexander Shishkin
2023-01-19 17:06 ` [PATCH 1/2] PCI/MSI: Cache the MSIX table size Alexander Shishkin
2023-01-22  9:00   ` Leon Romanovsky
2023-01-22 10:57     ` Marc Zyngier
2023-01-22 15:34       ` David Laight
2023-01-24 11:59       ` Alexander Shishkin
2023-01-22 10:57     ` Greg KH
2023-01-23 10:22       ` Jonathan Cameron [this message]
2023-01-24 11:52     ` Alexander Shishkin
2023-01-24 12:10       ` Leon Romanovsky
2023-01-24 12:42         ` Alexander Shishkin
2023-01-24 12:59           ` Leon Romanovsky
2023-01-24 15:28             ` Alexander Shishkin
2023-01-24 15:32       ` Greg KH
2023-01-25 12:33         ` Reshetova, Elena
2023-01-19 17:06 ` [PATCH 2/2] PCI/MSI: Validate device supplied MSI table offset and size Alexander Shishkin

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