From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D408DC77B7E for ; Sat, 22 Apr 2023 11:39:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229644AbjDVLjV (ORCPT ); Sat, 22 Apr 2023 07:39:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36290 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229451AbjDVLjU (ORCPT ); Sat, 22 Apr 2023 07:39:20 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B27BB1BF2; Sat, 22 Apr 2023 04:39:19 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 42FB260180; Sat, 22 Apr 2023 11:39:19 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 7FC5EC433D2; Sat, 22 Apr 2023 11:39:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1682163558; bh=pK0qgiNlLboL2fI/esuWJM9FvkpFccUxCjSyFGuRaz0=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=SLs28FaD8rt1EkkaYryi0jB/vsv8K1XClDsIyh7vk72HwII7dCc1vyIHiL7k4DvDH /W7KH5e8R2/mbWK+OydUsjJPonSYrSzS2wizwuNn/vUGewGqzsOSPNgxIWq3E5Iqxm 9fUgOKE+rC1Bf6IOMSk++ak3h+nlxijvtZXleqUMmUqZGJvU3VmiGi4jEfPLfmYngF rU5VP1GFDJxDYifFyj+fFkM1VrhuqL11qCO9y1JbNmZRlBr7vzUHuhwOfPxxikMpiB 8spvI7t3SBNIex6WqhvNXXgorEEaAfPnQUao2z7sWCtd0+Z0UPRBbplNcU7m8hauyl rqA6ZXUY4vOrw== Date: Sat, 22 Apr 2023 17:09:08 +0530 From: Manivannan Sadhasivam To: Yoshihiro Shimoda Cc: jingoohan1@gmail.com, gustavo.pimentel@synopsys.com, fancer.lancer@gmail.com, lpieralisi@kernel.org, robh+dt@kernel.org, kw@linux.com, bhelgaas@google.com, kishon@kernel.org, marek.vasut+renesas@gmail.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org Subject: Re: [PATCH v13 09/22] PCI: dwc: Add support for triggering INTx IRQs Message-ID: <20230422113908.GF4769@thinkpad> References: <20230418122403.3178462-1-yoshihiro.shimoda.uh@renesas.com> <20230418122403.3178462-10-yoshihiro.shimoda.uh@renesas.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20230418122403.3178462-10-yoshihiro.shimoda.uh@renesas.com> Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org On Tue, Apr 18, 2023 at 09:23:50PM +0900, Yoshihiro Shimoda wrote: It's good to add "endpoint drivers" in subject as below: PCI: dwc: Add support for triggering INTx IRQs from endpoint drivers > Add support for triggering INTx IRQs by using outbound iATU. > Outbound iATU is utilized to send assert and de-assert INTx TLPs. > The message is generated based on the payloadless Msg TLP with type > 0x14, where 0x4 is the routing code implying the Terminate at > Receiver message. The message code is specified as b1000xx for > the INTx assertion and b1001xx for the INTx de-assertion. > > Signed-off-by: Yoshihiro Shimoda > --- > .../pci/controller/dwc/pcie-designware-ep.c | 70 +++++++++++++++++-- > drivers/pci/controller/dwc/pcie-designware.h | 2 + > 2 files changed, 68 insertions(+), 4 deletions(-) > > diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c > index 96375b0aba82..304ed093f551 100644 > --- a/drivers/pci/controller/dwc/pcie-designware-ep.c > +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c > @@ -6,6 +6,7 @@ > * Author: Kishon Vijay Abraham I > */ > > +#include > #include > #include > > @@ -485,14 +486,62 @@ static const struct pci_epc_ops epc_ops = { > .get_features = dw_pcie_ep_get_features, > }; > > +static int dw_pcie_ep_send_msg(struct dw_pcie_ep *ep, u8 func_no, u8 code, > + u8 routing) > +{ > + struct dw_pcie_outbound_atu atu = { 0 }; > + struct pci_epc *epc = ep->epc; > + int ret; > + > + atu.func_no = func_no; > + atu.code = code; > + atu.routing = routing; > + atu.type = PCIE_ATU_TYPE_MSG; > + atu.cpu_addr = ep->intx_mem_phys; > + atu.size = epc->mem->window.page_size; Newline here. > + ret = dw_pcie_ep_outbound_atu(ep, &atu); > + if (ret) > + return ret; > + > + writel(0, ep->intx_mem); > + > + dw_pcie_ep_unmap_addr(epc, func_no, 0, ep->intx_mem_phys); > + > + return 0; > +} > + > +static int __dw_pcie_ep_raise_intx_irq(struct dw_pcie_ep *ep, u8 func_no, > + int intx) > +{ > + int ret; > + > + ret = dw_pcie_ep_send_msg(ep, func_no, PCI_CODE_ASSERT_INTA + intx, > + PCI_MSG_ROUTING_LOCAL); > + if (ret) > + return ret; > + > + /* > + * The documents of PCIe and the controller don't mention how long > + * the INTx should be asserted. If 10 usec, sometimes it failed. > + * So, asserted for 50 usec. > + */ > + usleep_range(50, 100); > + > + return dw_pcie_ep_send_msg(ep, func_no, PCI_CODE_DEASSERT_INTA + intx, > + PCI_MSG_ROUTING_LOCAL); > +} > + > int dw_pcie_ep_raise_intx_irq(struct dw_pcie_ep *ep, u8 func_no) > { > struct dw_pcie *pci = to_dw_pcie_from_ep(ep); > struct device *dev = pci->dev; > > - dev_err(dev, "EP cannot trigger INTx IRQs\n"); > + if (!ep->intx_mem) { > + dev_err(dev, "EP cannot trigger INTx IRQs\n"); INTx not supported. > + return -EINVAL; -ENOTSUPP - Mani > + } > > - return -EINVAL; > + return __dw_pcie_ep_raise_intx_irq(ep, func_no, 0); > } > EXPORT_SYMBOL_GPL(dw_pcie_ep_raise_intx_irq); > > @@ -623,6 +672,10 @@ void dw_pcie_ep_exit(struct dw_pcie_ep *ep) > > dw_pcie_edma_remove(pci); > > + if (ep->intx_mem) > + pci_epc_mem_free_addr(epc, ep->intx_mem_phys, ep->intx_mem, > + epc->mem->window.page_size); > + > pci_epc_mem_free_addr(epc, ep->msi_mem_phys, ep->msi_mem, > epc->mem->window.page_size); > > @@ -794,9 +847,14 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep) > goto err_exit_epc_mem; > } > > + ep->intx_mem = pci_epc_mem_alloc_addr(epc, &ep->intx_mem_phys, > + epc->mem->window.page_size); > + if (!ep->intx_mem) > + dev_warn(dev, "Failed to reserve memory for INTx\n"); > + > ret = dw_pcie_edma_detect(pci); > if (ret) > - goto err_free_epc_mem; > + goto err_free_epc_mem_intx; > > if (ep->ops->get_features) { > epc_features = ep->ops->get_features(ep); > @@ -813,7 +871,11 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep) > err_remove_edma: > dw_pcie_edma_remove(pci); > > -err_free_epc_mem: > +err_free_epc_mem_intx: > + if (ep->intx_mem) > + pci_epc_mem_free_addr(epc, ep->intx_mem_phys, ep->intx_mem, > + epc->mem->window.page_size); > + > pci_epc_mem_free_addr(epc, ep->msi_mem_phys, ep->msi_mem, > epc->mem->window.page_size); > > diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h > index 954d504890a1..8c08159ea08e 100644 > --- a/drivers/pci/controller/dwc/pcie-designware.h > +++ b/drivers/pci/controller/dwc/pcie-designware.h > @@ -369,6 +369,8 @@ struct dw_pcie_ep { > unsigned long *ob_window_map; > void __iomem *msi_mem; > phys_addr_t msi_mem_phys; > + void __iomem *intx_mem; > + phys_addr_t intx_mem_phys; > struct pci_epf_bar *epf_bar[PCI_STD_NUM_BARS]; > }; > > -- > 2.25.1 > -- மணிவண்ணன் சதாசிவம்