From: Bjorn Helgaas <helgaas@kernel.org>
To: Dominic Rath <rath@ibv-augsburg.de>
Cc: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org,
tjoseph@cadence.com, bhelgaas@google.com, lpieralisi@kernel.org,
nm@ti.com, vigneshr@ti.com, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org,
christian.gmeiner@gmail.com, bahle@ibv-augsburg.de
Subject: Re: [PATCH v2 1/3] dt-bindings: phy: cadence-torrent: Add latency properties
Date: Thu, 27 Apr 2023 13:30:40 -0500 [thread overview]
Message-ID: <20230427183040.GA263395@bhelgaas> (raw)
In-Reply-To: <20230427055032.85015-2-rath@ibv-augsburg.de>
On Thu, Apr 27, 2023 at 07:50:30AM +0200, Dominic Rath wrote:
> From: Alexander Bahle <bahle@ibv-augsburg.de>
>
> Add "tx-phy-latency-ps" and "rx-phy-latency-ps" DT bindings for
> setting the PCIe PHY latencies.
> The properties expect a list of uint32 PHY latencies in picoseconds for
> every supported speed starting at PCIe Gen1, e.g.:
>
> tx-phy-latency-ps = <100000 200000>; /* Gen1: 100ns, Gen2: 200ns */
> rx-phy-latency-ps = <150000 250000>; /* Gen1: 150ns, Gen2: 250ns */
Are these things that could/should be described in a more generic
place? They don't look necessarily Cadence-specific.
Bjorn
next prev parent reply other threads:[~2023-04-27 18:30 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-04-27 5:50 [PATCH v2 0/3] Cadence PCIe PHY latency for PTM Dominic Rath
2023-04-27 5:50 ` [PATCH v2 1/3] dt-bindings: phy: cadence-torrent: Add latency properties Dominic Rath
2023-04-27 18:30 ` Bjorn Helgaas [this message]
2023-05-09 15:31 ` Christian Gmeiner
2023-05-09 21:57 ` Bjorn Helgaas
2023-05-10 7:08 ` Krzysztof Kozlowski
2023-05-10 21:12 ` Bjorn Helgaas
2023-05-30 8:19 ` Christian Gmeiner
2023-04-27 5:50 ` [PATCH v2 2/3] PCI: cadence: Use DT bindings to set PHY latencies Dominic Rath
2023-05-04 11:33 ` Verma, Achal
2023-05-30 8:20 ` Christian Gmeiner
2023-04-27 5:50 ` [PATCH v2 3/3] arm64: dts: ti: k3-am64: Add PCIe PHY latency DT binding Dominic Rath
2023-05-09 15:27 ` Christian Gmeiner
2023-05-30 8:21 ` [PATCH v2 0/3] Cadence PCIe PHY latency for PTM Christian Gmeiner
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20230427183040.GA263395@bhelgaas \
--to=helgaas@kernel.org \
--cc=bahle@ibv-augsburg.de \
--cc=bhelgaas@google.com \
--cc=christian.gmeiner@gmail.com \
--cc=devicetree@vger.kernel.org \
--cc=krzysztof.kozlowski+dt@linaro.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-pci@vger.kernel.org \
--cc=lpieralisi@kernel.org \
--cc=nm@ti.com \
--cc=rath@ibv-augsburg.de \
--cc=robh+dt@kernel.org \
--cc=tjoseph@cadence.com \
--cc=vigneshr@ti.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).