From: Ajay Agarwal <ajayagarwal@google.com>
To: Bjorn Helgaas <bhelgaas@google.com>,
Kuppuswamy Sathyanarayanan
<sathyanarayanan.kuppuswamy@linux.intel.com>,
Vidya Sagar <vidyas@nvidia.com>,
Nikhil Devshatwar <nikhilnd@google.com>,
Manu Gautam <manugautam@google.com>,
"David E. Box" <david.e.box@linux.intel.com>,
Kai-Heng Feng <kai.heng.feng@canonical.com>,
Michael Bottini <michael.a.bottini@linux.intel.com>
Cc: linux-pci@vger.kernel.org, Ajay Agarwal <ajayagarwal@google.com>
Subject: [PATCH v2 4/5] PCI/ASPM: Rename L1.2 specific functions
Date: Wed, 3 May 2023 01:01:39 +0530 [thread overview]
Message-ID: <20230502193140.1062470-5-ajayagarwal@google.com> (raw)
In-Reply-To: <20230502193140.1062470-1-ajayagarwal@google.com>
The functions aspm_calc_l1ss_info() and calc_l1ss_pwron() perform
calculations and register programming specific to L1.2 state.
Rename them to aspm_calc_l12_info() and calc_l12_pwron()
respectively.
Signed-off-by: Ajay Agarwal <ajayagarwal@google.com>
---
Changelog since v1:
- New patch to rename L1.2 specific functions
drivers/pci/pcie/aspm.c | 14 +++++++-------
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c
index 7c9935f331f1..db7c369a0544 100644
--- a/drivers/pci/pcie/aspm.c
+++ b/drivers/pci/pcie/aspm.c
@@ -337,7 +337,7 @@ static u32 calc_l1_acceptable(u32 encoding)
}
/* Convert L1SS T_pwr encoding to usec */
-static u32 calc_l1ss_pwron(struct pci_dev *pdev, u32 scale, u32 val)
+static u32 calc_l12_pwron(struct pci_dev *pdev, u32 scale, u32 val)
{
switch (scale) {
case 0:
@@ -471,7 +471,7 @@ static void pci_clear_and_set_dword(struct pci_dev *pdev, int pos,
}
/* Calculate L1.2 PM substate timing parameters */
-static void aspm_calc_l1ss_info(struct pcie_link_state *link,
+static void aspm_calc_l12_info(struct pcie_link_state *link,
u32 parent_l1ss_cap, u32 child_l1ss_cap)
{
struct pci_dev *child = link->downstream, *parent = link->pdev;
@@ -495,13 +495,13 @@ static void aspm_calc_l1ss_info(struct pcie_link_state *link,
val2 = (child_l1ss_cap & PCI_L1SS_CAP_P_PWR_ON_VALUE) >> 19;
scale2 = (child_l1ss_cap & PCI_L1SS_CAP_P_PWR_ON_SCALE) >> 16;
- if (calc_l1ss_pwron(parent, scale1, val1) >
- calc_l1ss_pwron(child, scale2, val2)) {
+ if (calc_l12_pwron(parent, scale1, val1) >
+ calc_l12_pwron(child, scale2, val2)) {
ctl2 |= scale1 | (val1 << 3);
- t_power_on = calc_l1ss_pwron(parent, scale1, val1);
+ t_power_on = calc_l12_pwron(parent, scale1, val1);
} else {
ctl2 |= scale2 | (val2 << 3);
- t_power_on = calc_l1ss_pwron(child, scale2, val2);
+ t_power_on = calc_l12_pwron(child, scale2, val2);
}
/*
@@ -617,7 +617,7 @@ static void aspm_l1ss_init(struct pcie_link_state *link)
link->aspm_enabled |= ASPM_STATE_L1_2_PCIPM;
if (link->aspm_support & ASPM_STATE_L1SS)
- aspm_calc_l1ss_info(link, parent_l1ss_cap, child_l1ss_cap);
+ aspm_calc_l12_info(link, parent_l1ss_cap, child_l1ss_cap);
}
static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist)
--
2.40.1.495.gc816e09b53d-goog
next prev parent reply other threads:[~2023-05-02 19:32 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-02 19:31 [PATCH v2 0/5] ASPM: aspm_disable/default state handling fixes Ajay Agarwal
2023-05-02 19:31 ` [PATCH v2 1/5] PCI/ASPM: Disable ASPM_STATE_L1 only when class driver disables L1 ASPM Ajay Agarwal
2023-05-03 1:10 ` Sathyanarayanan Kuppuswamy
2023-05-04 8:28 ` Ajay Agarwal
2023-05-02 19:31 ` [PATCH v2 2/5] PCI/ASPM: Set ASPM_STATE_L1 only when driver enables L1.0 Ajay Agarwal
2023-05-03 1:17 ` Sathyanarayanan Kuppuswamy
2023-05-04 8:30 ` Ajay Agarwal
2023-05-02 19:31 ` [PATCH v2 3/5] PCI/ASPM: Set ASPM_STATE_L1 when driver enables L1ss Ajay Agarwal
2023-05-03 1:18 ` Sathyanarayanan Kuppuswamy
2023-05-04 8:31 ` Ajay Agarwal
2023-05-02 19:31 ` Ajay Agarwal [this message]
2023-05-02 19:31 ` [PATCH v2 5/5] PCI/ASPM: Remove unnecessary ASPM_STATE_L1SS check Ajay Agarwal
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