Re: [PATCH 5/8] PCI: qcom: Do not advertise hotplug capability for IP v2.3.2

[Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>]

On Sat, May 06, 2023 at 04:01:43PM +0200, Konrad Dybcio wrote:
> 
> 
> On 6.05.2023 14:04, Dmitry Baryshkov wrote:
> > On 06/05/2023 10:31, Manivannan Sadhasivam wrote:
> >> SoCs making use of Qcom PCIe controller IP v2.3.2 do not support hotplug
> >> functionality. But the hotplug capability bit is set by default in the
> >> hardware. This causes the kernel PCI core to register hotplug service for
> >> the controller and send hotplug commands to it. But those commands will
> >> timeout generating messages as below during boot and suspend/resume.
> >>
> >> [    5.782159] pcieport 0001:00:00.0: pciehp: Timeout on hotplug command 0x03c0 (issued 2020 msec ago)
> >> [    5.810161] pcieport 0001:00:00.0: pciehp: Timeout on hotplug command 0x03c0 (issued 2048 msec ago)
> >> [    7.838162] pcieport 0001:00:00.0: pciehp: Timeout on hotplug command 0x07c0 (issued 2020 msec ago)
> >> [    7.870159] pcieport 0001:00:00.0: pciehp: Timeout on hotplug command 0x07c0 (issued 2052 msec ago)
> >>
> >> This not only spams the console output but also induces a delay of a
> >> couple of seconds. To fix this issue, let's clear the HPC bit in
> >> PCI_EXP_SLTCAP register as a part of the post init sequence to not
> >> advertise the hotplug capability for the controller.
> >>
> >> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> >> ---
> >>   drivers/pci/controller/dwc/pcie-qcom.c | 10 ++++++++++
> >>   1 file changed, 10 insertions(+)
> >>
> >> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
> >> index 3d5b3ce9e2da..33353be396ec 100644
> >> --- a/drivers/pci/controller/dwc/pcie-qcom.c
> >> +++ b/drivers/pci/controller/dwc/pcie-qcom.c
> >> @@ -579,6 +579,8 @@ static int qcom_pcie_init_2_3_2(struct qcom_pcie *pcie)
> >>     static int qcom_pcie_post_init_2_3_2(struct qcom_pcie *pcie)
> >>   {
> >> +    struct dw_pcie *pci = pcie->pci;
> >> +    u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
> >>       u32 val;
> >>         /* enable PCIe clocks and resets */
> >> @@ -602,6 +604,14 @@ static int qcom_pcie_post_init_2_3_2(struct qcom_pcie *pcie)
> >>       val |= EN;
> >>       writel(val, pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2);
> >>   +    dw_pcie_dbi_ro_wr_en(pci);
> >> +
> >> +    val = readl(pci->dbi_base + offset + PCI_EXP_SLTCAP);
> >> +    val &= ~PCI_EXP_SLTCAP_HPC;
> >> +    writel(val, pci->dbi_base + offset + PCI_EXP_SLTCAP);
> >> +
> >> +    dw_pcie_dbi_ro_wr_dis(pci);
> >> +
> > 
> > Seeing this code again and again makes me wonder if we should have a separate function for this.
> Moreover, is there no generic rmw type function for readl+writel?
> 

No rmw as of now. But it could be added to reduce boilerplate code. But it
should be part of separate cleanup series though.

- Mani

> Konrad
> > 

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