[PATCH] PCI/DPC: Apply PIO log size quirk to Intel Ice Lake Root Ports too

[PATCH] PCI/DPC: Apply PIO log size quirk to Intel Ice Lake Root Ports too

[Mika Westerberg]

Commit 5459c0b70467 ("PCI/DPC: Quirk PIO log size for certain Intel Root
Ports") added quirk for Tiger and Alder Lake Root Ports but missed that
the same issue exists also in the previous generation, Ice Lake, Root
Ports.

For this reason apply the quirk for Ice Lake Root Ports as well.

Reported-by: Mark Blakeney <mark.blakeney@bullet-systems.net>
Closes: https://bugzilla.kernel.org/show_bug.cgi?id=209943
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
---
 drivers/pci/quirks.c | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index b0304fc97c22..8206228a95e1 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -6006,8 +6006,9 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56c1, aspm_l1_acceptable_latency
 
 #ifdef CONFIG_PCIE_DPC
 /*
- * Intel Tiger Lake and Alder Lake BIOS has a bug that clears the DPC
- * RP PIO Log Size of the integrated Thunderbolt PCIe Root Ports.
+ * Intel Ice Lake, Tiger Lake and Alder Lake BIOS has a bug that clears
+ * the DPC RP PIO Log Size of the integrated Thunderbolt PCIe Root
+ * Ports.
  */
 static void dpc_log_size(struct pci_dev *dev)
 {
@@ -6030,6 +6031,10 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x461f, dpc_log_size);
 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x462f, dpc_log_size);
 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x463f, dpc_log_size);
 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x466e, dpc_log_size);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x8a1d, dpc_log_size);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x8a1f, dpc_log_size);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x8a21, dpc_log_size);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x8a23, dpc_log_size);
 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a23, dpc_log_size);
 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a25, dpc_log_size);
 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a27, dpc_log_size);
-- 
2.39.2

Re: [PATCH] PCI/DPC: Apply PIO log size quirk to Intel Ice Lake Root Ports too

[Bjorn Helgaas]

On Thu, May 11, 2023 at 03:19:05PM +0300, Mika Westerberg wrote:
> Commit 5459c0b70467 ("PCI/DPC: Quirk PIO log size for certain Intel Root
> Ports") added quirk for Tiger and Alder Lake Root Ports but missed that
> the same issue exists also in the previous generation, Ice Lake, Root
> Ports.
> 
> For this reason apply the quirk for Ice Lake Root Ports as well.
> 
> Reported-by: Mark Blakeney <mark.blakeney@bullet-systems.net>
> Closes: https://bugzilla.kernel.org/show_bug.cgi?id=209943
> Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>

Applied to for-linus for v6.4, thanks!

I edited the commit log slightly:

    PCI/DPC: Quirk PIO log size for Intel Ice Lake Root Ports

    Commit 5459c0b70467 ("PCI/DPC: Quirk PIO log size for certain Intel Root
    Ports") added quirks for Tiger and Alder Lake Root Ports but missed that
    the same issue exists also in the previous generation, Ice Lake.

    Apply the quirk for Ice Lake Root Ports as well.  This prevents kernel
    complaints like:

      DPC: RP PIO log size 0 is invalid

    and also enables the DPC driver to dump the RP PIO Log registers when DPC
    is triggered.

    [bhelgaas: add dmesg warning and RP PIO Log dump info]

> ---
>  drivers/pci/quirks.c | 9 +++++++--
>  1 file changed, 7 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
> index b0304fc97c22..8206228a95e1 100644
> --- a/drivers/pci/quirks.c
> +++ b/drivers/pci/quirks.c
> @@ -6006,8 +6006,9 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56c1, aspm_l1_acceptable_latency
>  
>  #ifdef CONFIG_PCIE_DPC
>  /*
> - * Intel Tiger Lake and Alder Lake BIOS has a bug that clears the DPC
> - * RP PIO Log Size of the integrated Thunderbolt PCIe Root Ports.
> + * Intel Ice Lake, Tiger Lake and Alder Lake BIOS has a bug that clears
> + * the DPC RP PIO Log Size of the integrated Thunderbolt PCIe Root
> + * Ports.
>   */
>  static void dpc_log_size(struct pci_dev *dev)
>  {
> @@ -6030,6 +6031,10 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x461f, dpc_log_size);
>  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x462f, dpc_log_size);
>  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x463f, dpc_log_size);
>  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x466e, dpc_log_size);
> +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x8a1d, dpc_log_size);
> +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x8a1f, dpc_log_size);
> +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x8a21, dpc_log_size);
> +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x8a23, dpc_log_size);
>  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a23, dpc_log_size);
>  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a25, dpc_log_size);
>  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a27, dpc_log_size);
> -- 
> 2.39.2
>