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From: Jonathan Cameron <Jonathan.Cameron@Huawei.com>
To: Smita Koralahalli <Smita.KoralahalliChannabasappa@amd.com>
Cc: <linux-pci@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
	<linux-cxl@vger.kernel.org>, Bjorn Helgaas <bhelgaas@google.com>,
	<oohall@gmail.com>, Lukas Wunner <lukas@wunner.de>,
	"Kuppuswamy Sathyanarayanan" 
	<sathyanarayanan.kuppuswamy@linux.intel.com>,
	"Mahesh J Salgaonkar" <mahesh@linux.ibm.com>,
	Alison Schofield <alison.schofield@intel.com>,
	Vishal Verma <vishal.l.verma@intel.com>,
	"Ira Weiny" <ira.weiny@intel.com>,
	Ben Widawsky <bwidawsk@kernel.org>,
	"Dan Williams" <dan.j.williams@intel.com>,
	Yazen Ghannam <yazen.ghannam@amd.com>,
	Terry Bowman <terry.bowman@amd.com>,
	Robert Richter <rrichter@amd.com>
Subject: Re: [PATCH v3 3/3] cxl/pci: Replace host_bridge->native_aer with pcie_aer_is_native()
Date: Fri, 4 Aug 2023 13:14:54 +0100	[thread overview]
Message-ID: <20230804131454.00000622@Huawei.com> (raw)
In-Reply-To: <20230803230129.127590-4-Smita.KoralahalliChannabasappa@amd.com>

On Thu, 3 Aug 2023 23:01:29 +0000
Smita Koralahalli <Smita.KoralahalliChannabasappa@amd.com> wrote:

> Use pcie_aer_is_native() to determine the native AER ownership as the
> usage of host_bride->native_aer does not cover command line override of
> AER ownership.
> 
> Signed-off-by: Smita Koralahalli <Smita.KoralahalliChannabasappa@amd.com>
> Reviewed-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
> Reviewed-by: Robert Richter <rrichter@amd.com>
I hope there aren't systems getting this wrong but make sense to support
same override as for other cases.

Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>

> ---
> v2:
> 	Replaced pcie_aer_is_native() at a later stage for automated
> 	backports.
> v3:
> 	Added more context to commit message.
> 	Added "Reviewed-by" tag.
> ---
>  drivers/cxl/pci.c | 3 +--
>  1 file changed, 1 insertion(+), 2 deletions(-)
> 
> diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c
> index 2323169b6e5f..44a21ab7add5 100644
> --- a/drivers/cxl/pci.c
> +++ b/drivers/cxl/pci.c
> @@ -529,7 +529,6 @@ static int cxl_pci_setup_regs(struct pci_dev *pdev, enum cxl_regloc_type type,
>  
>  static int cxl_pci_ras_unmask(struct pci_dev *pdev)
>  {
> -	struct pci_host_bridge *host_bridge = pci_find_host_bridge(pdev->bus);
>  	struct cxl_dev_state *cxlds = pci_get_drvdata(pdev);
>  	void __iomem *addr;
>  	u32 orig_val, val, mask;
> @@ -542,7 +541,7 @@ static int cxl_pci_ras_unmask(struct pci_dev *pdev)
>  	}
>  
>  	/* BIOS has PCIe AER error control */
> -	if (!host_bridge->native_aer)
> +	if (!pcie_aer_is_native(pdev))
>  		return 0;
>  
>  	rc = pcie_capability_read_word(pdev, PCI_EXP_DEVCTL, &cap);


  reply	other threads:[~2023-08-04 12:15 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-08-03 23:01 [PATCH v3 0/3] PCI/AER, CXL: Fix appropriate _OSC check for CXL RAS Cap Smita Koralahalli
2023-08-03 23:01 ` [PATCH v3 1/3] cxl/pci: Fix appropriate checking for _OSC while handling CXL RAS registers Smita Koralahalli
2023-08-04 12:09   ` Jonathan Cameron
2023-08-16 18:06     ` Dave Jiang
2023-08-16 21:33       ` Smita Koralahalli
2023-08-16 21:36         ` Smita Koralahalli
2023-08-16 21:39         ` Dave Jiang
2023-08-03 23:01 ` [PATCH v3 2/3] PCI/AER: Export pcie_aer_is_native() Smita Koralahalli
2023-08-04 12:13   ` Jonathan Cameron
2023-08-16 18:07   ` Dave Jiang
2023-08-03 23:01 ` [PATCH v3 3/3] cxl/pci: Replace host_bridge->native_aer with pcie_aer_is_native() Smita Koralahalli
2023-08-04 12:14   ` Jonathan Cameron [this message]
2023-08-16 18:08   ` Dave Jiang

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