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From: Bjorn Helgaas <helgaas@kernel.org>
To: Andy Shevchenko <andriy.shevchenko@intel.com>
Cc: Bartosz Pawlowski <bartosz.pawlowski@intel.com>,
	linux-pci@vger.kernel.org, bhelgaas@google.com,
	Sheena Mohan <sheenamo@google.com>,
	Aahil Awatramani <aahila@google.com>,
	Justin Tai <justai@google.com>,
	joel.a.gibson@intel.com, emil.s.tantilov@intel.com,
	gaurav.s.emmanuel@intel.com, mike.conover@intel.com,
	shaopeng.he@intel.com, anthony.l.nguyen@intel.com,
	pavan.kumar.linga@intel.com,
	Alexander Lobakin <aleksander.lobakin@intel.com>
Subject: Re: [PATCH 2/2] PCI: Disable ATS for specific Intel IPU E2000 devices
Date: Wed, 6 Sep 2023 15:13:29 -0500	[thread overview]
Message-ID: <20230906201329.GA237399@bhelgaas> (raw)
In-Reply-To: <ZPjaU2czatpVm9Xs@smile.fi.intel.com>

On Wed, Sep 06, 2023 at 11:00:19PM +0300, Andy Shevchenko wrote:
> On Wed, Sep 06, 2023 at 10:59:20PM +0300, Andy Shevchenko wrote:
> > On Wed, Sep 06, 2023 at 02:06:23PM -0500, Bjorn Helgaas wrote:
> > > On Wed, Aug 16, 2023 at 05:21:15PM +0000, Bartosz Pawlowski wrote:
> 
> ...
> 
> > > > +/*
> > > > + * Intel IPU E2000 revisions before C0 implement incorrect endianness
> > > > + * in ATS Invalidate Request message body. Although there is existing software
> > > > + * workaround for this issue, it is not functionally complete (no 5-lvl paging
> > > > + * support) and it requires changes in all IOMMU implementations supporting
> > > > + * ATS. Therefore, disabling ATS seems to be more reasonable.
> > > 
> > > Can we reference the commit that added the existing software
> > > workaround?
> 
> > See below.
> 
> Oh, I meant the second question here, i.e.
> 
> > > It sounds like systems that (a) don't require 5-level paging and (b)
> > > use an IOMMU implementation that include the appropriate changes might
> > > still be able to use ATS?  Is there a way for them to do that?
> 
> ^^^ this one.

Sorry, I'm missing your point here.

The comment mentions an existing partial software workaround.
Presumably that was added by some commit, and it would be helpful to
know which one.

The comment also suggests that if the software workaround were
completed (or if a system didn't require 5-level paging) and it had
related changes to its IOMMU driver, we could still use ATS even on
hardware with this defect.

So I'm wondering if there's a way for an IOMMU driver that has the
required changes and can tell that we're not using 5-level paging can
override this quirk that disables ATS.

Maybe we want to unconditionally disable ATS on these broken devices.
In that case, I think we should just completely drop the comments
about the software workaround and IOMMU driver changes because they
wouldn't be relevant.

> > > > + */
> > > > +static void quirk_intel_e2000_no_ats(struct pci_dev *pdev)
> > > > +{
> > 
> > > > +	if (pdev->revision < 0x20)
> > 
> > Isn't it the answer to your question?
> > 
> > > > +		quirk_no_ats(pdev);
> > > > +}
> 
> -- 
> With Best Regards,
> Andy Shevchenko
> 
> 

  reply	other threads:[~2023-09-06 20:13 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-08-16 17:21 [PATCH 0/2] PCI: Disable ATS for specific Intel IPU E2000 devices Bartosz Pawlowski
2023-08-16 17:21 ` [PATCH 1/2] PCI: Extract ATS disabling to a helper function Bartosz Pawlowski
2023-08-16 17:21 ` [PATCH 2/2] PCI: Disable ATS for specific Intel IPU E2000 devices Bartosz Pawlowski
2023-08-16 17:39   ` Bjorn Helgaas
2023-08-17  9:52     ` Andy Shevchenko
2023-08-17 10:02       ` Bartosz Pawlowski
2023-08-21 15:04       ` Alexander Lobakin
2023-09-06 19:06   ` Bjorn Helgaas
2023-09-06 19:59     ` Andy Shevchenko
2023-09-06 20:00       ` Andy Shevchenko
2023-09-06 20:13         ` Bjorn Helgaas [this message]
2023-09-06 20:56           ` Andy Shevchenko
2023-09-07 14:29           ` Bartosz Pawlowski
     [not found] <CADWJPTsm7XUMR94aLAg_o5TyMPQxXGwi++_9LtQVbhsi7A0_QA@mail.gmail.com>
2023-08-16 20:17 ` Bjorn Helgaas

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