Linux PCI subsystem development
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From: Lukas Wunner <lukas@wunner.de>
To: "Schroeder, Chad" <CSchroeder@sonifi.com>
Cc: "bhelgaas@google.com" <bhelgaas@google.com>,
	"linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>
Subject: Re: PCIe device issue since v6.1.16
Date: Tue, 19 Sep 2023 16:59:21 +0200	[thread overview]
Message-ID: <20230919145921.GA8609@wunner.de> (raw)
In-Reply-To: <DM6PR16MB2844903E34CAB910082DF019B1FAA@DM6PR16MB2844.namprd16.prod.outlook.com>

Hi Chad,

On Tue, Sep 19, 2023 at 02:17:29PM +0000, Schroeder, Chad wrote:
> 	After researching the issue, I found the commit that lead system error:
> 
> 	https://lore.kernel.org/all/da77c92796b99ec568bd070cbe4725074a117038.1673769517.git.lukas@wunner.de/
> 
> 	Specifically, this removal:
> 
> 	- Drop an unnecessary 1 sec delay from pci_reset_secondary_bus() which
> 	is now performed by pci_bridge_wait_for_secondary_bus().  A static
> 	delay this long is only necessary for Conventional PCI, so modern
> 	PCIe systems benefit from shorter reset times as a side effect.

Thanks for the report and sorry for the breakage.

This endpoint device only supports Gen1 speed (2.5GT/s) and does not support
Data Link Layer Link Active Reporting.  I have a suspicion that I neglected
to take this case into account in pci_bridge_wait_for_secondary_bus().

To better understand what's going on, could you also provide "lspci -vvv"
output of the parent bridge above 0000:65:00.0 (i.e. of the bridge whose
secondary bus is 65)?

Thanks!

Lukas

  reply	other threads:[~2023-09-19 14:59 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-09-19 14:17 PCIe device issue since v6.1.16 Schroeder, Chad
2023-09-19 14:59 ` Lukas Wunner [this message]
2023-09-19 15:08   ` Schroeder, Chad
2023-09-19 18:41     ` Lukas Wunner
2023-09-20 15:36       ` Schroeder, Chad

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