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From: Bjorn Helgaas <helgaas@kernel.org>
To: Jim Quinlan <james.quinlan@broadcom.com>
Cc: linux-pci@vger.kernel.org,
	"Nicolas Saenz Julienne" <nsaenz@kernel.org>,
	"Bjorn Helgaas" <bhelgaas@google.com>,
	"Lorenzo Pieralisi" <lorenzo.pieralisi@arm.com>,
	"Cyril Brulebois" <kibi@debian.org>,
	"Phil Elwell" <phil@raspberrypi.com>,
	bcm-kernel-feedback-list@broadcom.com,
	"Florian Fainelli" <florian.fainelli@broadcom.com>,
	"Jim Quinlan" <jim2101024@gmail.com>,
	"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
	"Krzysztof Wilczyński" <kw@linux.com>,
	"Rob Herring" <robh@kernel.org>,
	"moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE"
	<linux-rpi-kernel@lists.infradead.org>,
	"moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE"
	<linux-arm-kernel@lists.infradead.org>,
	"open list" <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v7 3/3] PCI: brcmstb: Set higher value for internal bus timeout
Date: Thu, 9 Nov 2023 15:27:22 -0600	[thread overview]
Message-ID: <20231109212722.GA492431@bhelgaas> (raw)
In-Reply-To: <20231109191355.27738-4-james.quinlan@broadcom.com>

On Thu, Nov 09, 2023 at 02:13:54PM -0500, Jim Quinlan wrote:
> During long periods of the PCIe RC HW being in an L1SS sleep state, there
> may be a timeout on an internal bus access, even though there may not be
> any PCIe access involved.  Such a timeout will cause a subsequent CPU
> abort.
> 
> Signed-off-by: Jim Quinlan <james.quinlan@broadcom.com>
> ---
>  drivers/pci/controller/pcie-brcmstb.c | 16 ++++++++++++++++
>  1 file changed, 16 insertions(+)
> 
> diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c
> index f45c5d0168d3..f82a3e1a843a 100644
> --- a/drivers/pci/controller/pcie-brcmstb.c
> +++ b/drivers/pci/controller/pcie-brcmstb.c
> @@ -1031,6 +1031,21 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie)
>  	return 0;
>  }
>  
> +/*
> + * This extends the timeout period for an access to an internal bus.  This
> + * access timeout may occur during L1SS sleep periods, even without the
> + * presence of a PCIe access.
> + */
> +static void brcm_extend_rbus_timeout(struct brcm_pcie *pcie)
> +{
> +	/* TIMEOUT register is two registers before RGR1_SW_INIT_1 */
> +	const unsigned int REG_OFFSET = PCIE_RGR1_SW_INIT_1(pcie) - 8;
> +	u32 timeout_us = 4000000; /* 4 seconds, our setting for L1SS */
> +
> +	/* Each unit in timeout register is 1/216,000,000 seconds */
> +	writel(216 * timeout_us, pcie->base + REG_OFFSET);
> +}
> +
>  static void brcm_config_clkreq(struct brcm_pcie *pcie)
>  {
>  	static const char err_msg[] = "invalid 'brcm,clkreq-mode' DT string\n";
> @@ -1067,6 +1082,7 @@ static void brcm_config_clkreq(struct brcm_pcie *pcie)
>  		 * atypical and should happen only with older devices.
>  		 */
>  		clkreq_cntl |= PCIE_MISC_HARD_PCIE_HARD_DEBUG_L1SS_ENABLE_MASK;
> +		brcm_extend_rbus_timeout(pcie);

It looks like this should be squashed into the previous patch, which
added brcm_config_clkreq().  Otherwise there's a bisection hole where
somebody testing at the previous patch could see the CPU abort.

>  	} else {
>  		/*
>  		 * "safe" -- No power savings; refclk is driven by RC

  reply	other threads:[~2023-11-09 21:27 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-11-09 19:13 [PATCH v7 0/3] PCI: brcmstb: Configure appropriate HW CLKREQ# mode Jim Quinlan
2023-11-09 19:13 ` [PATCH v7 1/3] dt-bindings: PCI: brcmstb: Add property "brcm,clkreq-mode" Jim Quinlan
2023-11-09 21:33   ` Bjorn Helgaas
2023-11-09 19:13 ` [PATCH v7 2/3] PCI: brcmstb: Configure HW CLKREQ# mode appropriate for downstream device Jim Quinlan
2023-11-09 21:27   ` Bjorn Helgaas
2023-11-09 22:06     ` Jim Quinlan
2023-11-09 22:31       ` Bjorn Helgaas
2023-11-10 13:01         ` Jim Quinlan
2023-11-10 14:39           ` Bjorn Helgaas
2023-11-09 19:13 ` [PATCH v7 3/3] PCI: brcmstb: Set higher value for internal bus timeout Jim Quinlan
2023-11-09 21:27   ` Bjorn Helgaas [this message]
2023-11-13 17:36 ` [PATCH v7 0/3] PCI: brcmstb: Configure appropriate HW CLKREQ# mode Florian Fainelli

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