From: Mario Limonciello <mario.limonciello@amd.com>
To: "Karol Herbst" <kherbst@redhat.com>,
"Lyude Paul" <lyude@redhat.com>,
"Alex Deucher" <alexander.deucher@amd.com>,
"Christian König" <christian.koenig@amd.com>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Mika Westerberg" <mika.westerberg@linux.intel.com>,
"Lukas Wunner" <lukas@wunner.de>
Cc: "Danilo Krummrich" <dakr@redhat.com>,
"David Airlie" <airlied@gmail.com>,
"Daniel Vetter" <daniel@ffwll.ch>,
"Xinhui Pan" <Xinhui.Pan@amd.com>,
"Rafael J . Wysocki" <rafael@kernel.org>,
"Ilpo Järvinen" <ilpo.jarvinen@linux.intel.com>,
"Pali Rohár" <pali@kernel.org>, "Marek Behún" <kabel@kernel.org>,
"Maciej W . Rozycki" <macro@orcam.me.uk>,
"Manivannan Sadhasivam" <mani@kernel.org>,
"Mario Limonciello" <mario.limonciello@amd.com>,
"open list:DRM DRIVER FOR NVIDIA GEFORCE/QUADRO GPUS"
<dri-devel@lists.freedesktop.org>,
"open list:DRM DRIVER FOR NVIDIA GEFORCE/QUADRO GPUS"
<nouveau@lists.freedesktop.org>,
"open list" <linux-kernel@vger.kernel.org>,
"open list:RADEON and AMDGPU DRM DRIVERS"
<amd-gfx@lists.freedesktop.org>,
"open list:PCI SUBSYSTEM" <linux-pci@vger.kernel.org>,
"open list:ACPI" <linux-acpi@vger.kernel.org>
Subject: [PATCH v3 6/7] PCI: Split up some logic in pcie_bandwidth_available() to separate function
Date: Tue, 14 Nov 2023 14:07:54 -0600 [thread overview]
Message-ID: <20231114200755.14911-7-mario.limonciello@amd.com> (raw)
In-Reply-To: <20231114200755.14911-1-mario.limonciello@amd.com>
The logic to calculate bandwidth limits may be used at multiple call sites
so split it up into its own static function instead.
No intended functional changes.
Suggested-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
---
v2->v3:
* Split from previous patch version
---
drivers/pci/pci.c | 60 +++++++++++++++++++++++++++--------------------
1 file changed, 34 insertions(+), 26 deletions(-)
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index 55bc3576a985..0ff7883cc774 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -6224,6 +6224,38 @@ int pcie_set_mps(struct pci_dev *dev, int mps)
}
EXPORT_SYMBOL(pcie_set_mps);
+static u32 pcie_calc_bw_limits(struct pci_dev *dev, u32 bw,
+ struct pci_dev **limiting_dev,
+ enum pci_bus_speed *speed,
+ enum pcie_link_width *width)
+{
+ enum pcie_link_width next_width;
+ enum pci_bus_speed next_speed;
+ u32 next_bw;
+ u16 lnksta;
+
+ pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta);
+
+ next_speed = pcie_link_speed[FIELD_GET(PCI_EXP_LNKSTA_CLS, lnksta)];
+ next_width = FIELD_GET(PCI_EXP_LNKSTA_NLW, lnksta);
+
+ next_bw = next_width * PCIE_SPEED2MBS_ENC(next_speed);
+
+ /* Check if current device limits the total bandwidth */
+ if (!bw || next_bw <= bw) {
+ bw = next_bw;
+
+ if (limiting_dev)
+ *limiting_dev = dev;
+ if (speed)
+ *speed = next_speed;
+ if (width)
+ *width = next_width;
+ }
+
+ return bw;
+}
+
/**
* pcie_bandwidth_available - determine minimum link settings of a PCIe
* device and its bandwidth limitation
@@ -6242,39 +6274,15 @@ u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev,
enum pci_bus_speed *speed,
enum pcie_link_width *width)
{
- u16 lnksta;
- enum pci_bus_speed next_speed;
- enum pcie_link_width next_width;
- u32 bw, next_bw;
+ u32 bw = 0;
if (speed)
*speed = PCI_SPEED_UNKNOWN;
if (width)
*width = PCIE_LNK_WIDTH_UNKNOWN;
- bw = 0;
-
while (dev) {
- pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta);
-
- next_speed = pcie_link_speed[FIELD_GET(PCI_EXP_LNKSTA_CLS,
- lnksta)];
- next_width = FIELD_GET(PCI_EXP_LNKSTA_NLW, lnksta);
-
- next_bw = next_width * PCIE_SPEED2MBS_ENC(next_speed);
-
- /* Check if current device limits the total bandwidth */
- if (!bw || next_bw <= bw) {
- bw = next_bw;
-
- if (limiting_dev)
- *limiting_dev = dev;
- if (speed)
- *speed = next_speed;
- if (width)
- *width = next_width;
- }
-
+ bw = pcie_calc_bw_limits(dev, bw, limiting_dev, speed, width);
dev = pci_upstream_bridge(dev);
}
--
2.34.1
next prev parent reply other threads:[~2023-11-14 20:08 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-11-14 20:07 [PATCH v3 0/7] Improvements to pcie_bandwidth_available() for eGPUs Mario Limonciello
2023-11-14 20:07 ` [PATCH v3 1/7] drm/nouveau: Switch from pci_is_thunderbolt_attached() to dev_is_removable() Mario Limonciello
2023-11-16 12:50 ` Ilpo Järvinen
2023-11-14 20:07 ` [PATCH v3 2/7] drm/radeon: " Mario Limonciello
2023-11-15 9:27 ` Christian König
2023-11-14 20:07 ` [PATCH v3 3/7] PCI: Drop pci_is_thunderbolt_attached() Mario Limonciello
2023-11-16 12:51 ` Ilpo Järvinen
2023-11-14 20:07 ` [PATCH v3 4/7] PCI: pciehp: Move check for is_thunderbolt into a quirk Mario Limonciello
2023-11-16 12:30 ` Ilpo Järvinen
2023-11-14 20:07 ` [PATCH v3 5/7] PCI: ACPI: Detect PCIe root ports that are used for tunneling Mario Limonciello
2023-11-15 10:40 ` Mika Westerberg
2023-11-15 17:08 ` Mario Limonciello
2023-11-16 9:00 ` Mika Westerberg
2023-11-14 20:07 ` Mario Limonciello [this message]
2023-11-16 13:02 ` [PATCH v3 6/7] PCI: Split up some logic in pcie_bandwidth_available() to separate function Ilpo Järvinen
2023-11-14 20:07 ` [PATCH v3 7/7] PCI: Exclude PCIe ports used for virtual links in pcie_bandwidth_available() Mario Limonciello
2023-11-15 3:23 ` Lazar, Lijo
2023-11-15 17:04 ` Mario Limonciello
2023-11-15 21:09 ` Mario Limonciello
2023-11-16 4:33 ` Lazar, Lijo
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