Re: [PATCH v3 06/10] PCI: Cache PCIe device's Supported Speed Vector

[Lukas Wunner <lukas@wunner.de>]

On Fri, Sep 29, 2023 at 02:57:19PM +0300, Ilpo Järvinen wrote:
> The Supported Link Speeds Vector in the Link Capabilities Register 2
> corresponds to the bus below on Root Ports and Downstream Ports,
> whereas it corresponds to the bus above on Upstream Ports and
> Endpoints.

It would be good to add a pointer to the spec here.  I think the
relevant section is PCIe r6.1 sec 7.5.3.18 which says:

 "Supported Link Speeds Vector - This field indicates the supported
  Link speed(s) of the associated Port."
                       ^^^^^^^^^^^^^^^

Obviously the associated port is upstream on a Switch Upstream Port
or Endpoint, whereas it is downstream on a Switch Downstream Port
or Root Port.

Come to think of it, what about edge cases such as RCiEPs?


> Only the former is currently cached in pcie_bus_speeds in
> the struct pci_bus. The link speeds that are supported is the
> intersection of these two.

I'm wondering if caching both is actually necessary.  Why not cache
just the intersection?  Do we need either of the two somewhere?


> Store the device's Supported Link Speeds Vector into the struct pci_bus
> when the Function 0 is enumerated (the Multi-Function Devices must have
> same speeds the same for all Functions) to be easily able to calculate
> the intersection of Supported Link Speeds.

Might want to add an explanation what you're going to need this for,
I assume it's accessed frequently by the bandwidth throttling driver
in a subsequent patch?

Thanks,

Lukas