From: Lukas Wunner <lukas@wunner.de>
To: "Ilpo Järvinen" <ilpo.jarvinen@linux.intel.com>
Cc: linux-pci@vger.kernel.org, Bjorn Helgaas <helgaas@kernel.org>,
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
Rob Herring <robh@kernel.org>,
Krzysztof Wilczy??ski <kw@linux.com>,
Alexandru Gagniuc <mr.nuke.me@gmail.com>,
Krishna chaitanya chundru <quic_krichai@quicinc.com>,
Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>,
"Rafael J . Wysocki" <rafael@kernel.org>,
linux-pm@vger.kernel.org, Bjorn Helgaas <bhelgaas@google.com>,
LKML <linux-kernel@vger.kernel.org>,
Alex Deucher <alexdeucher@gmail.com>,
Daniel Lezcano <daniel.lezcano@linaro.org>,
Amit Kucheria <amitk@kernel.org>, Zhang Rui <rui.zhang@intel.com>
Subject: Re: [PATCH v3 08/10] PCI/bwctrl: Add "controller" part into PCIe bwctrl
Date: Wed, 3 Jan 2024 17:40:06 +0100 [thread overview]
Message-ID: <20240103164006.GA3463@wunner.de> (raw)
In-Reply-To: <b56bb460-7876-272a-23ce-83d1dab212b2@linux.intel.com>
On Mon, Jan 01, 2024 at 08:12:43PM +0200, Ilpo Järvinen wrote:
> On Sat, 30 Dec 2023, Lukas Wunner wrote:
> > On Fri, Sep 29, 2023 at 02:57:21PM +0300, Ilpo Järvinen wrote:
> > > --- a/drivers/pci/pcie/bwctrl.c
> > > +static u16 speed2lnkctl2(enum pci_bus_speed speed)
> > > +{
> > > + static const u16 speed_conv[] = {
> > > + [PCIE_SPEED_2_5GT] = PCI_EXP_LNKCTL2_TLS_2_5GT,
> > > + [PCIE_SPEED_5_0GT] = PCI_EXP_LNKCTL2_TLS_5_0GT,
> > > + [PCIE_SPEED_8_0GT] = PCI_EXP_LNKCTL2_TLS_8_0GT,
> > > + [PCIE_SPEED_16_0GT] = PCI_EXP_LNKCTL2_TLS_16_0GT,
> > > + [PCIE_SPEED_32_0GT] = PCI_EXP_LNKCTL2_TLS_32_0GT,
> > > + [PCIE_SPEED_64_0GT] = PCI_EXP_LNKCTL2_TLS_64_0GT,
> > > + };
> >
> > Looks like this could be a u8 array to save a little bit of memory.
> >
> > Also, this seems to duplicate pcie_link_speed[] defined in probe.c.
>
> It's not the same. pcie_link_speed[] is indexed by a different thing
Ah, missed that. Those various conversion functions are confusing.
> > > + dev_speeds = READ_ONCE(bus->pcie_dev_speeds);
> >
> > Hm, why is the compiler barrier needed?
>
> It's probably an overkill but there could be a checker which finds this
> read is not protected by anything while the value could get updated
> concurrectly
Why should it be updated? It's a static value cached on enumeration
and never changed AFAICS.
> If the value selected cannot be set because of endpoint no longer being
> there, the other parts of the code will detect that.
If the endpoint is hot-unplugged, the link is down, so retraining
the link will fail.
If the device is replaced concurrently to retraining then you may
try to retrain to a speed which is too fast or too slow for the new
device. Maybe it's necessary to cope with that? Basically find the
pci_dev on the bus with the device/function id and check if the pci_dev
pointer still points to the same location. Another idea would be to
hook up bwctrl with pciehp so that pciehp tells bwctrl the device is
gone and any speed changes should be aborted. We've hooked up DPC
with pciehp in a similar way.
> So if I just add a comment to this line why there's the data race and keep
> it as is?
I'd just drop the READ_ONCE() here if there's not a good reason for it.
Thanks,
Lukas
next prev parent reply other threads:[~2024-01-03 16:40 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-29 11:57 [PATCH v3 00/10] Add PCIe Bandwidth Controller Ilpo Järvinen
2023-09-29 11:57 ` [PATCH v3 01/10] PCI: Protect Link Control 2 Register with RMW locking Ilpo Järvinen
2023-12-30 10:33 ` Lukas Wunner
2023-09-29 11:57 ` [PATCH v3 02/10] drm/radeon: Use RMW accessors for changing LNKCTL2 Ilpo Järvinen
2023-09-29 11:57 ` [PATCH v3 03/10] drm/amdgpu: " Ilpo Järvinen
2023-09-29 11:57 ` [PATCH v3 04/10] RDMA/hfi1: " Ilpo Järvinen
2023-09-29 13:03 ` Dean Luick
2023-09-29 11:57 ` [PATCH v3 05/10] PCI: Store all PCIe Supported Link Speeds Ilpo Järvinen
2023-12-30 11:45 ` Lukas Wunner
2023-12-30 19:30 ` Lukas Wunner
2024-01-01 16:26 ` Ilpo Järvinen
2024-01-01 16:40 ` Lukas Wunner
2024-01-01 16:53 ` Ilpo Järvinen
2023-09-29 11:57 ` [PATCH v3 06/10] PCI: Cache PCIe device's Supported Speed Vector Ilpo Järvinen
2023-12-30 15:19 ` Lukas Wunner
2024-01-01 18:31 ` Ilpo Järvinen
2024-01-03 16:51 ` Lukas Wunner
2023-09-29 11:57 ` [PATCH v3 07/10] PCI/LINK: Re-add BW notification portdrv as PCIe BW controller Ilpo Järvinen
2023-12-30 15:58 ` Lukas Wunner
2024-01-01 17:37 ` Ilpo Järvinen
2024-01-01 18:11 ` Lukas Wunner
2023-09-29 11:57 ` [PATCH v3 08/10] PCI/bwctrl: Add "controller" part into PCIe bwctrl Ilpo Järvinen
2023-12-30 18:49 ` Lukas Wunner
2024-01-01 18:12 ` Ilpo Järvinen
2024-01-03 16:40 ` Lukas Wunner [this message]
2023-09-29 11:57 ` [PATCH v3 09/10] thermal: Add PCIe cooling driver Ilpo Järvinen
2023-12-30 19:08 ` Lukas Wunner
2024-01-01 16:39 ` Ilpo Järvinen
2023-09-29 11:57 ` [PATCH v3 10/10] selftests/pcie_bwctrl: Create selftests Ilpo Järvinen
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