Re: [PATCH v7 12/16] PCI: imx6: Add iMX95 PCIe support

Manivannan Sadhasivam
2024-01-07T05:51:13Z

On Wed, Dec 27, 2023 at 01:27:23PM -0500, Frank Li wrote:

Mention 'RC' in subject.

> Add iMX95 PCIe basic root complex function support.
>

Add iMX95 PCIe Root Complex support.

> Signed-off-by: Frank Li <Frank.Li@nxp.com>
> ---
>
> Notes:
> Change from v1 to v3
> - none
>
> drivers/pci/controller/dwc/pci-imx6.c | 90 +++++++++++++++++++++++++--
> 1 file changed, 85 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
> index d66a2db53bdb7..9e60ab6f1885a 100644
> --- a/drivers/pci/controller/dwc/pci-imx6.c
> +++ b/drivers/pci/controller/dwc/pci-imx6.c
> @@ -42,6 +42,25 @@
> #define IMX8MQ_GPR_PCIE_VREG_BYPASS BIT(12)
> #define IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE GENMASK(11, 8)
>
> +#define IMX95_PCIE_PHY_GEN_CTRL 0x0
> +#define IMX95_PCIE_REF_USE_PAD BIT(17)
> +
> +#define IMX95_PCIE_PHY_MPLLA_CTRL 0x10
> +#define IMX95_PCIE_PHY_MPLL_STATE BIT(30)
> +
> +#define IMX95_PCIE_SS_RW_REG_0 0xf0
> +#define IMX95_PCIE_REF_CLKEN BIT(23)
> +#define IMX95_PCIE_PHY_CR_PARA_SEL BIT(9)
> +
> +#define IMX95_PE0_GEN_CTRL_1 0x1050
> +#define IMX95_PCIE_DEVICE_TYPE GENMASK(3, 0)
> +
> +#define IMX95_PE0_GEN_CTRL_3 0x1058
> +#define IMX95_PCIE_LTSSM_EN BIT(0)
> +
> +#define IMX95_PE0_PM_STS 0x1064
> +#define IMX95_PCIE_PM_LINKST_IN_L2 BIT(14)
> +
> #define to_imx6_pcie(x) dev_get_drvdata((x)->dev)
>
> enum imx6_pcie_variants {
> @@ -52,6 +71,7 @@ enum imx6_pcie_variants {
> IMX8MQ,
> IMX8MM,
> IMX8MP,
> + IMX95,
> IMX8MQ_EP,
> IMX8MM_EP,
> IMX8MP_EP,
> @@ -63,6 +83,7 @@ enum imx6_pcie_variants {
> #define IMX6_PCIE_FLAG_HAS_PHY BIT(3)
> #define IMX6_PCIE_FLAG_HAS_APP_RESET BIT(4)
> #define IMX6_PCIE_FLAG_HAS_PHY_RESET BIT(5)
> +#define IMX6_PCIE_FLAG_HAS_SERDES BIT(6)
>
> #define imx6_check_flag(pci, val) (pci->drvdata->flags & val)
>
> @@ -179,6 +200,24 @@ static unsigned int imx6_pcie_grp_offset(const struct imx6_pcie *imx6_pcie)
> return imx6_pcie->controller_id == 1 ? IOMUXC_GPR16 : IOMUXC_GPR14;
> }
>
> +static int imx95_pcie_init_phy(struct imx6_pcie *imx6_pcie)
> +{
> + regmap_update_bits(imx6_pcie->iomuxc_gpr,
> + IMX95_PCIE_SS_RW_REG_0,
> + IMX95_PCIE_PHY_CR_PARA_SEL,
> + IMX95_PCIE_PHY_CR_PARA_SEL);
> +
> + regmap_update_bits(imx6_pcie->iomuxc_gpr,
> + IMX95_PCIE_PHY_GEN_CTRL,
> + IMX95_PCIE_REF_USE_PAD, 0);
> + regmap_update_bits(imx6_pcie->iomuxc_gpr,
> + IMX95_PCIE_SS_RW_REG_0,
> + IMX95_PCIE_REF_CLKEN,
> + IMX95_PCIE_REF_CLKEN);
> +
> + return 0;
> +}
> +
> static void imx6_pcie_configure_type(struct imx6_pcie *imx6_pcie)
> {
> const struct imx6_pcie_drvdata *drvdata = imx6_pcie->drvdata;
> @@ -579,6 +618,7 @@ static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie)
> IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16);
> break;
> case IMX7D:
> + case IMX95:
> break;
> case IMX8MM:
> case IMX8MM_EP:
> @@ -696,10 +736,19 @@ static int imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie)
> {
> struct dw_pcie *pci = imx6_pcie->pci;
> struct device *dev = pci->dev;
> + u32 val;
>
> reset_control_deassert(imx6_pcie->pciephy_reset);
>
> switch (imx6_pcie->drvdata->variant) {
> + case IMX95:
> + /* Polling the MPLL_STATE */
> + if (regmap_read_poll_timeout(imx6_pcie->iomuxc_gpr,
> + IMX95_PCIE_PHY_MPLLA_CTRL, val,
> + val & IMX95_PCIE_PHY_MPLL_STATE,
> + 10, 10000))
> + dev_err(dev, "PCIe PLL lock timeout\n");

You should return err here because, if core deassert is not performed then the
core itself cannot be used.

> + break;
> case IMX7D:
> /* Workaround for ERR010728, failure of PCI-e PLL VCO to
> * oscillate, especially when cold. This turns off "Duty-cycle
> @@ -1281,12 +1330,32 @@ static int imx6_pcie_probe(struct platform_device *pdev)
> return PTR_ERR(imx6_pcie->turnoff_reset);
> }
>
> + if (imx6_pcie->drvdata->gpr) {
> /* Grab GPR config register range */
> - imx6_pcie->iomuxc_gpr =
> - syscon_regmap_lookup_by_compatible(imx6_pcie->drvdata->gpr);
> - if (IS_ERR(imx6_pcie->iomuxc_gpr)) {
> - dev_err(dev, "unable to find iomuxc registers\n");
> - return PTR_ERR(imx6_pcie->iomuxc_gpr);
> + imx6_pcie->iomuxc_gpr =
> + syscon_regmap_lookup_by_compatible(imx6_pcie->drvdata->gpr);
> + if (IS_ERR(imx6_pcie->iomuxc_gpr))
> + return dev_err_probe(dev, PTR_ERR(imx6_pcie->iomuxc_gpr),
> + "unable to find iomuxc registers\n");
> + }
> +
> + if (imx6_check_flag(imx6_pcie, IMX6_PCIE_FLAG_HAS_SERDES)) {
> + void __iomem *off = devm_platform_ioremap_resource_byname(pdev, "app");
> +
> + if (IS_ERR(off))
> + return dev_err_probe(dev, PTR_ERR(off),
> + "unable to find serdes registers\n");
> +
> + static struct regmap_config regmap_config = {

const

- Mani

--
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