Re: [PATCH v7 14/16] PCI: imx6: Add epc_features in imx6_pcie_drvdata

Manivannan Sadhasivam
2024-01-07T06:16:56Z

On Wed, Dec 27, 2023 at 01:27:25PM -0500, Frank Li wrote:
> The i.MX EP exhibits variations in epc_features among different EP
> configurations. This introduces the addition of epc_features in
> imx6_pcie_drvdata to accommodate these differences. It's important to note
> that there are no functional changes in this commit; instead, it lays the
> groundwork for supporting i.MX95 EP functions.
>
> Signed-off-by: Frank Li <Frank.Li@nxp.com>

Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>

- Mani

> ---
>
> Notes:
> Change from v5 to v6
> - add missed maxitems.
> - add comments about reuse linux,pci-domain as controller id.
> linux,pci-domain have not defined at PCI endpoint side.
>
> Change from v1 to v3
> - new patch at v3
>
> drivers/pci/controller/dwc/pci-imx6.c | 9 ++++++++-
> 1 file changed, 8 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
> index 4b2b9aafad1b4..6a58fd63a9dd2 100644
> --- a/drivers/pci/controller/dwc/pci-imx6.c
> +++ b/drivers/pci/controller/dwc/pci-imx6.c
> @@ -104,6 +104,7 @@ struct imx6_pcie_drvdata {
> const u32 ltssm_mask;
> const u32 mode_off[IMX6_PCIE_MAX_INSTANCES];
> const u32 mode_mask[IMX6_PCIE_MAX_INSTANCES];
> + const struct pci_epc_features *epc_features;
> int (*init_phy)(struct imx6_pcie *pcie);
> };
>
> @@ -1065,7 +1066,10 @@ static const struct pci_epc_features imx8m_pcie_epc_features = {
> static const struct pci_epc_features*
> imx6_pcie_ep_get_features(struct dw_pcie_ep *ep)
> {
> - return &imx8m_pcie_epc_features;
> + struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> + struct imx6_pcie *imx6_pcie = to_imx6_pcie(pci);
> +
> + return imx6_pcie->drvdata->epc_features;
> }
>
> static const struct dw_pcie_ep_ops pcie_ep_ops = {
> @@ -1530,6 +1534,7 @@ static const struct imx6_pcie_drvdata drvdata[] = {
> .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
> .mode_off[1] = IOMUXC_GPR12,
> .mode_mask[1] = IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE,
> + .epc_features = &imx8m_pcie_epc_features,
> .init_phy = imx8mq_pcie_init_phy,
> },
> [IMX8MM_EP] = {
> @@ -1540,6 +1545,7 @@ static const struct imx6_pcie_drvdata drvdata[] = {
> .clk_names = {"pcie_bus", "pcie", "pcie_aux"},
> .mode_off[0] = IOMUXC_GPR12,
> .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
> + .epc_features = &imx8m_pcie_epc_features,
> },
> [IMX8MP_EP] = {
> .variant = IMX8MP_EP,
> @@ -1549,6 +1555,7 @@ static const struct imx6_pcie_drvdata drvdata[] = {
> .clk_names = {"pcie_bus", "pcie", "pcie_aux"},
> .mode_off[0] = IOMUXC_GPR12,
> .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
> + .epc_features = &imx8m_pcie_epc_features,
> },
> };
>
> --
> 2.34.1
>

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