[PATCH v1 2/3] PCI: dwc: add equalization settings for gen4

Shashank Babu Chinta Venkata
2024-03-01T05:13:07Z

GEN3_RELATED_OFFSET is being used as shadow register for generation4 and
generation5 data rates based on rate select mask settings on this register.
Select relevant mask and equalization settings for generation4 operation.

Signed-off-by: Shashank Babu Chinta Venkata <quic_schintav@quicinc.com>
---
drivers/pci/controller/dwc/pcie-qcom-cmn.c | 31 ++++++++++++++++++++++
drivers/pci/controller/dwc/pcie-qcom-cmn.h | 23 ++++++++++++++++
drivers/pci/controller/dwc/pcie-qcom-ep.c | 4 +++
drivers/pci/controller/dwc/pcie-qcom.c | 4 +++
4 files changed, 62 insertions(+)

diff --git a/drivers/pci/controller/dwc/pcie-qcom-cmn.c b/drivers/pci/controller/dwc/pcie-qcom-cmn.c
index 0f8d004fbc79..cfdc04eef78c 100644
--- a/drivers/pci/controller/dwc/pcie-qcom-cmn.c
+++ b/drivers/pci/controller/dwc/pcie-qcom-cmn.c
@@ -18,6 +18,37 @@
#define QCOM_PCIE_LINK_SPEED_TO_BW(speed) \
Mbps_to_icc(PCIE_SPEED2MBS_ENC(pcie_link_speed[speed]))

+void qcom_pcie_cmn_set_gen4_eq_settings(struct dw_pcie *pci)
+{
+ u32 reg;
+
+ reg = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF);
+ reg &= ~GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL;
+ reg &= ~GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK;
+ reg |= (0x1 << GEN3_RELATED_OFF_RATE_SHADOW_SEL_SHIFT);
+ dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, reg);
+
+ reg = dw_pcie_readl_dbi(pci, GEN3_EQ_FB_MODE_DIR_CHANGE_OFF);
+ reg &= ~GEN3_EQ_FMDC_T_MIN_PHASE23_MASK;
+ reg &= ~GEN3_EQ_FMDC_N_EVALS_MASK;
+ reg |= (GEN3_EQ_FMDC_N_EVALS_VAL <<
+ GEN3_EQ_FMDC_N_EVALS_SHIFT);
+ reg &= ~GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA_MASK;
+ reg |= (GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA_VAL <<
+ GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA_SHIFT);
+ reg &= ~GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA_MASK;
+ reg |= (GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA_VAL <<
+ GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA_SHIFT);
+ dw_pcie_writel_dbi(pci, GEN3_EQ_FB_MODE_DIR_CHANGE_OFF, reg);
+
+ reg = dw_pcie_readl_dbi(pci, GEN3_EQ_CONTROL_OFF);
+ reg &= ~GEN3_EQ_CONTROL_OFF_FB_MODE_MASK;
+ reg &= ~GEN3_EQ_CONTROL_OFF_PHASE23_EXIT_MODE;
+ reg &= ~GEN3_EQ_CONTROL_OFF_FOM_INC_INITIAL_EVAL;
+ reg &= ~GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC_MASK;
+ dw_pcie_writel_dbi(pci, GEN3_EQ_CONTROL_OFF, reg);
+}
+EXPORT_SYMBOL_GPL(qcom_pcie_cmn_set_gen4_eq_settings);

int qcom_pcie_cmn_icc_get_resource(struct dw_pcie *pci, struct icc_path *icc_mem)
{
diff --git a/drivers/pci/controller/dwc/pcie-qcom-cmn.h b/drivers/pci/controller/dwc/pcie-qcom-cmn.h
index 8794dbd4775c..08e1bd179207 100644
--- a/drivers/pci/controller/dwc/pcie-qcom-cmn.h
+++ b/drivers/pci/controller/dwc/pcie-qcom-cmn.h
@@ -9,10 +9,29 @@
#include "../../pci.h"
#include "pcie-designware.h"

+#define GEN3_EQ_CONTROL_OFF 0x8a8
+#define GEN3_EQ_CONTROL_OFF_FB_MODE_MASK GENMASK(3, 0)
+#define GEN3_EQ_CONTROL_OFF_PHASE23_EXIT_MODE BIT(4)
+#define GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC_MASK GENMASK(23, 8)
+#define GEN3_EQ_CONTROL_OFF_FOM_INC_INITIAL_EVAL BIT(24)
+
+#define GEN3_EQ_FB_MODE_DIR_CHANGE_OFF 0x8ac
+#define GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA_VAL 0x5
+#define GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA_VAL 0x5
+#define GEN3_EQ_FMDC_N_EVALS_VAL 0xD
+#define GEN3_EQ_FMDC_T_MIN_PHASE23_MASK GENMASK(4, 0)
+#define GEN3_EQ_FMDC_N_EVALS_MASK GENMASK(9, 5)
+#define GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA_MASK GENMASK(13, 10)
+#define GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA_MASK GENMASK(17, 14)
+#define GEN3_EQ_FMDC_N_EVALS_SHIFT 5
+#define GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA_SHIFT 10
+#define GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA_SHIFT 14
+
#ifdef CONFIG_PCIE_QCOM_CMN
int qcom_pcie_cmn_icc_get_resource(struct dw_pcie *pci, struct icc_path *icc_mem);
int qcom_pcie_cmn_icc_init(struct dw_pcie *pci, struct icc_path *icc_mem);
void qcom_pcie_cmn_icc_update(struct dw_pcie *pci, struct icc_path *icc_mem);
+void qcom_pcie_cmn_set_gen4_eq_settings(struct dw_pcie *pci);
#else
static inline int qcom_pcie_cmn_icc_get_resource(struct dw_pcie *pci, struct icc_path *icc_mem)
{
@@ -27,4 +46,8 @@ static inline int qcom_pcie_cmn_icc_init(struct dw_pcie *pci, struct icc_path *i
static inline void qcom_pcie_cmn_icc_update(struct dw_pcie *pci, struct icc_path *icc_mem)
{
}
+
+static inline void qcom_pcie_cmn_set_gen4_eq_settings(struct dw_pcie *pci)
+{
+}
#endif
diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c
index ce6343426de8..0b169bcd081d 100644
--- a/drivers/pci/controller/dwc/pcie-qcom-ep.c
+++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c
@@ -438,6 +438,10 @@ static int qcom_pcie_perst_deassert(struct dw_pcie *pci)
goto err_disable_resources;
}

+ /* set Gen4 equalization settings */
+ if (pci->link_gen == 4)
+ qcom_pcie_cmn_set_gen4_eq_settings(pci);
+
/*
* The physical address of the MMIO region which is exposed as the BAR
* should be written to MHI BASE registers.
diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index 57a08294c561..ad0cd55da777 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -263,6 +263,10 @@ static int qcom_pcie_start_link(struct dw_pcie *pci)
{
struct qcom_pcie *pcie = to_qcom_pcie(pci);

+ /* set Gen4 equalization settings */
+ if (pci->link_gen == 4)
+ qcom_pcie_cmn_set_gen4_eq_settings(pci);
+
/* Enable Link Training state machine */
if (pcie->cfg->ops->ltssm_enable)
pcie->cfg->ops->ltssm_enable(pcie);
--
2.43.2