From: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
To: Mrinmay Sarkar <quic_msarkar@quicinc.com>
Cc: andersson@kernel.org, krzysztof.kozlowski+dt@linaro.org,
conor+dt@kernel.org, konrad.dybcio@linaro.org, robh@kernel.org,
quic_shazhuss@quicinc.com, quic_nitegupt@quicinc.com,
quic_ramkri@quicinc.com, quic_nayiluri@quicinc.com,
dmitry.baryshkov@linaro.org, quic_krichai@quicinc.com,
quic_vbadigan@quicinc.com, quic_schintav@quicinc.com,
"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
"Krzysztof Wilczyński" <kw@linux.com>,
"Bjorn Helgaas" <bhelgaas@google.com>,
linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org
Subject: Re: [PATCH v5 1/3] PCI: qcom: Enable cache coherency for SA8775P RC
Date: Mon, 4 Mar 2024 11:37:00 +0530 [thread overview]
Message-ID: <20240304060700.GD2647@thinkpad> (raw)
In-Reply-To: <1708697021-16877-2-git-send-email-quic_msarkar@quicinc.com>
On Fri, Feb 23, 2024 at 07:33:38PM +0530, Mrinmay Sarkar wrote:
Subject should be:
"PCI: qcom: Override NO_SNOOP attribute for SA8775P"
> Due to some hardware changes, SA8775P has set the NO_SNOOP attribute
> in its TLP for all the PCIe controllers. NO_SNOOP attribute when set,
> the requester is indicating that there no cache coherency issues exit
> for the addressed memory on the host i.e., memory is not cached. But
s/host/endpoint
> in reality, requester cannot assume this unless there is a complete
> control/visibility over the addressed memory on the host.
>
s/host/endpoint
> And worst case, if the memory is cached on the host, it may lead to
s/host/endpoint
> memory corruption issues. It should be noted that the caching of memory
> on the host is not solely dependent on the NO_SNOOP attribute in TLP.
>
s/host/endpoint
> So to avoid the corruption, this patch overrides the NO_SNOOP attribute
> by setting the PCIE_PARF_NO_SNOOP_OVERIDE register. This patch is not
> needed for other upstream supported platforms since they do not set
> NO_SNOOP attribute by default.
>
> 8775 has IP version 1.34.0 so intruduce a new cfg(cfg_1_34_0) for this
> platform. Assign enable_cache_snoop flag into struct qcom_pcie_cfg and
> set it true in cfg_1_34_0 and enable cache snooping if this particular
> flag is true.
>
> Signed-off-by: Mrinmay Sarkar <quic_msarkar@quicinc.com>
> ---
> drivers/pci/controller/dwc/pcie-qcom.c | 20 +++++++++++++++++++-
> 1 file changed, 19 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
> index 2ce2a3bd932b..872be7f7d7b3 100644
> --- a/drivers/pci/controller/dwc/pcie-qcom.c
> +++ b/drivers/pci/controller/dwc/pcie-qcom.c
> @@ -51,6 +51,7 @@
> #define PARF_SID_OFFSET 0x234
> #define PARF_BDF_TRANSLATE_CFG 0x24c
> #define PARF_SLV_ADDR_SPACE_SIZE 0x358
> +#define PARF_NO_SNOOP_OVERIDE 0x3d4
> #define PARF_DEVICE_TYPE 0x1000
> #define PARF_BDF_TO_SID_TABLE_N 0x2000
>
> @@ -117,6 +118,10 @@
> /* PARF_LTSSM register fields */
> #define LTSSM_EN BIT(8)
>
> +/* PARF_NO_SNOOP_OVERIDE register fields */
> +#define WR_NO_SNOOP_OVERIDE_EN BIT(1)
> +#define RD_NO_SNOOP_OVERIDE_EN BIT(3)
> +
> /* PARF_DEVICE_TYPE register fields */
> #define DEVICE_TYPE_RC 0x4
>
> @@ -229,6 +234,7 @@ struct qcom_pcie_ops {
>
Please add Kdoc comments for this struct. And describe the "override_no_snoop"
member as below:
"Override NO_SNOOP attribute in TLP to enable cache snooping"
> struct qcom_pcie_cfg {
> const struct qcom_pcie_ops *ops;
> + bool enable_cache_snoop;
Rename this to "override_no_snoop"
> };
>
> struct qcom_pcie {
> @@ -961,6 +967,13 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie)
>
> static int qcom_pcie_post_init_2_7_0(struct qcom_pcie *pcie)
> {
> + const struct qcom_pcie_cfg *pcie_cfg = pcie->cfg;
> +
> + /* Enable cache snooping for SA8775P */
Remove this comment in favor of Kdoc mentioned above.
- Mani
--
மணிவண்ணன் சதாசிவம்
next prev parent reply other threads:[~2024-03-04 6:07 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-02-23 14:03 [PATCH v5 0/3] arm64: qcom: sa8775p: add cache coherency support for SA8775P Mrinmay Sarkar
2024-02-23 14:03 ` [PATCH v5 1/3] PCI: qcom: Enable cache coherency for SA8775P RC Mrinmay Sarkar
2024-02-23 22:54 ` Bjorn Helgaas
2024-02-28 13:04 ` Mrinmay Sarkar
2024-02-28 15:02 ` Bjorn Helgaas
2024-02-28 17:14 ` Manivannan Sadhasivam
2024-02-28 17:39 ` Bjorn Helgaas
2024-02-28 18:45 ` Manivannan Sadhasivam
2024-02-28 19:34 ` Bjorn Helgaas
2024-03-04 6:00 ` Manivannan Sadhasivam
2024-03-04 6:07 ` Manivannan Sadhasivam [this message]
2024-02-23 14:03 ` [PATCH v5 2/3] PCI: qcom-ep: Enable cache coherency for SA8775P EP Mrinmay Sarkar
2024-02-24 0:07 ` Konrad Dybcio
2024-02-28 13:06 ` Mrinmay Sarkar
2024-02-23 14:03 ` [PATCH v5 3/3] arm64: dts: qcom: sa8775p: Mark PCIe EP controller as cache coherent Mrinmay Sarkar
2024-02-24 10:19 ` [PATCH v5 0/3] arm64: qcom: sa8775p: add cache coherency support for SA8775P Krzysztof Kozlowski
2024-02-28 13:07 ` Mrinmay Sarkar
2024-02-28 14:02 ` Krzysztof Kozlowski
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