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[209.17.68.221]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1ef0bada3efsm155625185ad.114.2024.05.17.04.27.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 May 2024 04:27:35 -0700 (PDT) Date: Fri, 17 May 2024 20:27:34 +0900 From: Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= To: Marek Vasut Cc: linux-pci@vger.kernel.org, Bjorn Helgaas , Lorenzo Pieralisi , Rob Herring , Yoshihiro Shimoda , linux-renesas-soc@vger.kernel.org Subject: Re: [PATCH] PCI: rcar: Demote WARN() to dev_warn_ratelimited() in rcar_pcie_wakeup() Message-ID: <20240517112734.GX202520@rocinante> References: <20240511235513.77301-1-marek.vasut+renesas@mailbox.org> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20240511235513.77301-1-marek.vasut+renesas@mailbox.org> Hello, > Avoid large backtrace, it is sufficient to warn the user that there has > been a link problem. Either the link has failed and the system is in need > of maintenance, or the link continues to work and user has been informed. > The message from the warning can be looked up in the sources. > > This makes an actual link issue less verbose. > > First of all, this controller has a limitation in that the controller > driver has to assist the hardware with transition to L1 link state by > writing L1IATN to PMCTRL register, the L1 and L0 link state switching > is not fully automatic on this controller. > > In case of an ASMedia ASM1062 PCIe SATA controller which does not support > ASPM, on entry to suspend or during platform pm_test, the SATA controller > enters D3hot state and the link enters L1 state. If the SATA controller > wakes up before rcar_pcie_wakeup() was called and returns to D0, the link > returns to L0 before the controller driver even started its transition to > L1 link state. At this point, the SATA controller did send an PM_ENTER_L1 > DLLP to the PCIe controller and the PCIe controller received it, and the > PCIe controller did set PMSR PMEL1RX bit. > > Once rcar_pcie_wakeup() is called, if the link is already back in L0 state > and PMEL1RX bit is set, the controller driver has no way to determine if > it should perform the link transition to L1 state, or treat the link as if > it is in L0 state. Currently the driver attempts to perform the transition > to L1 link state unconditionally, which in this specific case fails with a > PMSR L1FAEG poll timeout, however the link still works as it is already > back in L0 state. > > Reduce this warning verbosity. In case the link is really broken, the > rcar_pcie_config_access() would fail, otherwise it will succeed and any > system with this controller and ASM1062 can suspend without generating > a backtrace. Applied to controller/rcar, thank you! [1/1] PCI: rcar: Demote WARN() to dev_warn_ratelimited() in rcar_pcie_wakeup() https://git.kernel.org/pci/pci/c/a37647d5639b Krzysztof