From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from out-176.mta0.migadu.com (out-176.mta0.migadu.com [91.218.175.176]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AE66E158869 for ; Fri, 31 May 2024 16:13:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.218.175.176 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717172031; cv=none; b=QsTYKFtJ34MjwIhAYcQeuv+B/FfjA3d0kh2MEtB3JN+kd/nbtuANEX6YtYKN/fvspK9FW4Nt5YIyw1OtMB2NN5Rq25iaDreiJpW5zCUnwXJ4y1HXaE6BnYEaNUkYSbvl7Degju08BAOiSoHGC6VhPRHeMC22QUcshTOJeC6Ku8o= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717172031; c=relaxed/simple; bh=vZhBBVl8czJfcB3QyAXJ/jzdXjaM/KONvegUH9JNRgQ=; h=From:To:Cc:Subject:Date:Message-Id:MIME-Version:Content-Type; b=N1KwsHlFOYGNSauYNb8ixdlpuKF8vW2l3RuHsME7SyaSxirWVOfcEoMPD7In5KuOgpf/0dzbMTJ3p1ObnL441h7r7Nqb99zWijoMCfsJFNYH4t19a3znEdTP58DitabwL89terLbRVYnxRLHRhplQA+EVOMZteIP7dhGJyJZOck= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=dNvXwOiT; arc=none smtp.client-ip=91.218.175.176 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="dNvXwOiT" X-Envelope-To: lpieralisi@kernel.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1717172027; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=9pcEl9M55lrI6aQcGSoBDLIhIuk5i++OCOwZXRusXEo=; b=dNvXwOiTb/9FbHUiQ24hdOMu3t1DwGywelWdjk+2NUVmKRtBIpyCrrYtoSlW435aPZUImW xzraYG7o0qWposzy2mO2QwNEtTKiLsSZpRUvsA1c0szkKJfXdi0x+KGI5jPMEtlulrKYb4 b2gMAZs+ZkKiViisJ+mEtCNS0Dfh0Lc= X-Envelope-To: kw@linux.com X-Envelope-To: robh@kernel.org X-Envelope-To: linux-pci@vger.kernel.org X-Envelope-To: thippeswamy.havalige@amd.com X-Envelope-To: linux-arm-kernel@lists.infradead.org X-Envelope-To: markus.elfring@web.de X-Envelope-To: dan.carpenter@linaro.org X-Envelope-To: linux-kernel@vger.kernel.org X-Envelope-To: bhelgaas@google.com X-Envelope-To: michal.simek@amd.com X-Envelope-To: sean.anderson@linux.dev X-Envelope-To: bharat.kumar.gogada@xilinx.com X-Envelope-To: bharatku@xilinx.com X-Envelope-To: helgaas@kernel.org X-Envelope-To: conor+dt@kernel.org X-Envelope-To: krzysztof.kozlowski+dt@linaro.org X-Envelope-To: lorenzo.pieralisi@arm.com X-Envelope-To: michal.simek@xilinx.com X-Envelope-To: devicetree@vger.kernel.org X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. From: Sean Anderson To: Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Rob Herring , linux-pci@vger.kernel.org Cc: Thippeswamy Havalige , linux-arm-kernel@lists.infradead.org, Markus Elfring , Dan Carpenter , linux-kernel@vger.kernel.org, Bjorn Helgaas , Michal Simek , Sean Anderson , Bharat Kumar Gogada , Bharat Kumar Gogada , Bjorn Helgaas , Conor Dooley , Krzysztof Kozlowski , Lorenzo Pieralisi , Michal Simek , devicetree@vger.kernel.org Subject: [PATCH v4 0/7] PCI: xilinx-nwl: Add phy support Date: Fri, 31 May 2024 12:13:30 -0400 Message-Id: <20240531161337.864994-1-sean.anderson@linux.dev> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Migadu-Flow: FLOW_OUT Add phy subsystem support for the xilinx-nwl PCIe controller. This series also includes several small fixes and improvements. Changes in v4: - Clarify dt-bindings commit subject/message - Explain likely effects of the off-by-one error - Trim down UBSAN backtrace - Move if to after pci_host_probe - Remove if in err_phy - Fix error path in phy_enable skipping the first phy - Disable phys in reverse order - Use dev_err instead of WARN for errors Changes in v3: - Document phys property - Expand off-by-one commit message Changes in v2: - Remove phy-names - Add an example - Get phys by index and not by name Sean Anderson (7): dt-bindings: pci: xilinx-nwl: Add phys property PCI: xilinx-nwl: Fix off-by-one in IRQ handler PCI: xilinx-nwl: Fix register misspelling PCI: xilinx-nwl: Rate-limit misc interrupt messages PCI: xilinx-nwl: Clean up clock on probe failure/removal PCI: xilinx-nwl: Add phy support arm64: zynqmp: Add PCIe phys .../bindings/pci/xlnx,nwl-pcie.yaml | 7 + .../boot/dts/xilinx/zynqmp-zcu102-revA.dts | 1 + drivers/pci/controller/pcie-xilinx-nwl.c | 139 +++++++++++++++--- 3 files changed, 124 insertions(+), 23 deletions(-) -- 2.35.1.1320.gc452695387.dirty