Re: [PATCH v4 0/7] PCI: xilinx-nwl: Add phy support

Sean Anderson
2024-08-09T19:43:45Z

On 5/31/24 12:13, Sean Anderson wrote:
> Add phy subsystem support for the xilinx-nwl PCIe controller. This
> series also includes several small fixes and improvements.
>
> Changes in v4:
> - Clarify dt-bindings commit subject/message
> - Explain likely effects of the off-by-one error
> - Trim down UBSAN backtrace
> - Move if to after pci_host_probe
> - Remove if in err_phy
> - Fix error path in phy_enable skipping the first phy
> - Disable phys in reverse order
> - Use dev_err instead of WARN for errors
>
> Changes in v3:
> - Document phys property
> - Expand off-by-one commit message
>
> Changes in v2:
> - Remove phy-names
> - Add an example
> - Get phys by index and not by name
>
> Sean Anderson (7):
> dt-bindings: pci: xilinx-nwl: Add phys property
> PCI: xilinx-nwl: Fix off-by-one in IRQ handler
> PCI: xilinx-nwl: Fix register misspelling
> PCI: xilinx-nwl: Rate-limit misc interrupt messages
> PCI: xilinx-nwl: Clean up clock on probe failure/removal
> PCI: xilinx-nwl: Add phy support
> arm64: zynqmp: Add PCIe phys
>
> .../bindings/pci/xlnx,nwl-pcie.yaml | 7 +
> .../boot/dts/xilinx/zynqmp-zcu102-revA.dts | 1 +
> drivers/pci/controller/pcie-xilinx-nwl.c | 139 +++++++++++++++---
> 3 files changed, 124 insertions(+), 23 deletions(-)
>

ping.

--Sean