Re: [PATCH 2/2] PCI: xilinx-xdma: Add Xilinx QDMA Root Port driver

kernel test robot
2024-06-26T20:08:14Z

Hi Thippeswamy,

kernel test robot noticed the following build warnings:

[auto build test WARNING on pci/next]
[also build test WARNING on pci/for-linus linus/master v6.10-rc5 next-20240625]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url: https://github.com/intel-lab-lkp/linux/commits/Thippeswamy-Havalige/dt-bindings-PCI-xilinx-xdma-Add-schemas-for-Xilinx-QDMA-PCIe-Root-Port-Bridge/20240626-052852
base: https://git.kernel.org/pub/scm/linux/kernel/git/pci/pci.git next
patch link: https://lore.kernel.org/r/20240624104239.132159-3-thippesw%40amd.com
patch subject: [PATCH 2/2] PCI: xilinx-xdma: Add Xilinx QDMA Root Port driver
config: loongarch-allyesconfig (https://download.01.org/0day-ci/archive/20240627/202406270344.9nOuTH5k-lkp@intel.com/config)
compiler: loongarch64-linux-gcc (GCC) 13.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20240627/202406270344.9nOuTH5k-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202406270344.9nOuTH5k-lkp@intel.com/

All warnings (new ones prefixed by >>):

>> drivers/pci/controller/pcie-xilinx-dma-pl.c:130: warning: Function parameter or struct member 'cfg_base' not described in 'pl_dma_pcie'
>> drivers/pci/controller/pcie-xilinx-dma-pl.c:130: warning: Function parameter or struct member 'variant' not described in 'pl_dma_pcie'

vim +130 drivers/pci/controller/pcie-xilinx-dma-pl.c

8d786149d78c77 Thippeswamy Havalige 2023-10-03 101
8d786149d78c77 Thippeswamy Havalige 2023-10-03 102 /**
8d786149d78c77 Thippeswamy Havalige 2023-10-03 103 * struct pl_dma_pcie - PCIe port information
8d786149d78c77 Thippeswamy Havalige 2023-10-03 104 * @dev: Device pointer
8d786149d78c77 Thippeswamy Havalige 2023-10-03 105 * @reg_base: IO Mapped Register Base
8d786149d78c77 Thippeswamy Havalige 2023-10-03 106 * @irq: Interrupt number
8d786149d78c77 Thippeswamy Havalige 2023-10-03 107 * @cfg: Holds mappings of config space window
8d786149d78c77 Thippeswamy Havalige 2023-10-03 108 * @phys_reg_base: Physical address of reg base
8d786149d78c77 Thippeswamy Havalige 2023-10-03 109 * @intx_domain: Legacy IRQ domain pointer
8d786149d78c77 Thippeswamy Havalige 2023-10-03 110 * @pldma_domain: PL DMA IRQ domain pointer
8d786149d78c77 Thippeswamy Havalige 2023-10-03 111 * @resources: Bus Resources
8d786149d78c77 Thippeswamy Havalige 2023-10-03 112 * @msi: MSI information
8d786149d78c77 Thippeswamy Havalige 2023-10-03 113 * @intx_irq: INTx error interrupt number
8d786149d78c77 Thippeswamy Havalige 2023-10-03 114 * @lock: Lock protecting shared register access
8d786149d78c77 Thippeswamy Havalige 2023-10-03 115 */
8d786149d78c77 Thippeswamy Havalige 2023-10-03 116 struct pl_dma_pcie {
8d786149d78c77 Thippeswamy Havalige 2023-10-03 117 struct device *dev;
8d786149d78c77 Thippeswamy Havalige 2023-10-03 118 void __iomem *reg_base;
21ff31dc400101 Thippeswamy Havalige 2024-06-24 119 void __iomem *cfg_base;
8d786149d78c77 Thippeswamy Havalige 2023-10-03 120 int irq;
8d786149d78c77 Thippeswamy Havalige 2023-10-03 121 struct pci_config_window *cfg;
8d786149d78c77 Thippeswamy Havalige 2023-10-03 122 phys_addr_t phys_reg_base;
8d786149d78c77 Thippeswamy Havalige 2023-10-03 123 struct irq_domain *intx_domain;
8d786149d78c77 Thippeswamy Havalige 2023-10-03 124 struct irq_domain *pldma_domain;
8d786149d78c77 Thippeswamy Havalige 2023-10-03 125 struct list_head resources;
8d786149d78c77 Thippeswamy Havalige 2023-10-03 126 struct xilinx_msi msi;
8d786149d78c77 Thippeswamy Havalige 2023-10-03 127 int intx_irq;
8d786149d78c77 Thippeswamy Havalige 2023-10-03 128 raw_spinlock_t lock;
21ff31dc400101 Thippeswamy Havalige 2024-06-24 129 const struct xilinx_pl_dma_variant *variant;
8d786149d78c77 Thippeswamy Havalige 2023-10-03 @130 };
8d786149d78c77 Thippeswamy Havalige 2023-10-03 131

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