[pci:controller/rockchip 11/11] drivers/pci/controller/dwc/pcie-dw-rockchip.c:491:undefined reference to `pci_epc_init_notify'

[kernel test robot <lkp@intel.com>]

tree:   https://git.kernel.org/pub/scm/linux/kernel/git/pci/pci.git controller/rockchip
head:   246afbe0f6fca433d8d918b740719170b1b082cc
commit: 246afbe0f6fca433d8d918b740719170b1b082cc [11/11] PCI: dw-rockchip: Use pci_epc_init_notify() directly
config: loongarch-randconfig-r081-20240626 (https://download.01.org/0day-ci/archive/20240627/202406270721.a8SQi2hn-lkp@intel.com/config)
compiler: loongarch64-linux-gcc (GCC) 13.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20240627/202406270721.a8SQi2hn-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202406270721.a8SQi2hn-lkp@intel.com/

All errors (new ones prefixed by >>):

   loongarch64-linux-ld: drivers/pci/controller/dwc/pcie-designware-ep.o: in function `dw_pcie_ep_init_notify':
   drivers/pci/controller/dwc/pcie-designware-ep.c:26:(.text+0x1e4): undefined reference to `pci_epc_init_notify'
   loongarch64-linux-ld: drivers/pci/controller/dwc/pcie-designware-ep.o: in function `dw_pcie_ep_deinit':
   drivers/pci/controller/dwc/pcie-designware-ep.c:640:(.text+0x83c): undefined reference to `pci_epc_mem_free_addr'
   loongarch64-linux-ld: drivers/pci/controller/dwc/pcie-designware-ep.c:643:(.text+0x854): undefined reference to `pci_epc_mem_exit'
   loongarch64-linux-ld: drivers/pci/controller/dwc/pcie-designware-ep.o: in function `dw_pcie_ep_linkup':
   drivers/pci/controller/dwc/pcie-designware-ep.c:811:(.text+0x924): undefined reference to `pci_epc_linkup'
   loongarch64-linux-ld: drivers/pci/controller/dwc/pcie-designware-ep.o: in function `dw_pcie_ep_linkdown':
   drivers/pci/controller/dwc/pcie-designware-ep.c:836:(.text+0x964): undefined reference to `pci_epc_linkdown'
   loongarch64-linux-ld: drivers/pci/controller/dwc/pcie-designware-ep.o: in function `dw_pcie_ep_init':
   drivers/pci/controller/dwc/pcie-designware-ep.c:875:(.text+0xe90): undefined reference to `__devm_pci_epc_create'
   loongarch64-linux-ld: drivers/pci/controller/dwc/pcie-designware-ep.c:888:(.text+0xf20): undefined reference to `pci_epc_mem_init'
   loongarch64-linux-ld: drivers/pci/controller/dwc/pcie-designware-ep.c:895:(.text+0xf54): undefined reference to `pci_epc_mem_alloc_addr'
   loongarch64-linux-ld: drivers/pci/controller/dwc/pcie-designware-ep.c:906:(.text+0xf74): undefined reference to `pci_epc_mem_exit'
   loongarch64-linux-ld: drivers/pci/controller/dwc/pcie-dw-rockchip.o: in function `rockchip_pcie_configure_ep':
>> drivers/pci/controller/dwc/pcie-dw-rockchip.c:491:(.text+0x7cc): undefined reference to `pci_epc_init_notify'


vim +491 drivers/pci/controller/dwc/pcie-dw-rockchip.c

   441	
   442	static int rockchip_pcie_configure_ep(struct platform_device *pdev,
   443					      struct rockchip_pcie *rockchip)
   444	{
   445		struct device *dev = &pdev->dev;
   446		int irq, ret;
   447		u32 val;
   448	
   449		if (!IS_ENABLED(CONFIG_PCIE_ROCKCHIP_DW_EP))
   450			return -ENODEV;
   451	
   452		irq = platform_get_irq_byname(pdev, "sys");
   453		if (irq < 0) {
   454			dev_err(dev, "missing sys IRQ resource\n");
   455			return irq;
   456		}
   457	
   458		ret = devm_request_threaded_irq(dev, irq, NULL,
   459						rockchip_pcie_ep_sys_irq_thread,
   460						IRQF_ONESHOT, "pcie-sys", rockchip);
   461		if (ret) {
   462			dev_err(dev, "failed to request PCIe sys IRQ\n");
   463			return ret;
   464		}
   465	
   466		/* LTSSM enable control mode */
   467		val = HIWORD_UPDATE_BIT(PCIE_LTSSM_ENABLE_ENHANCE);
   468		rockchip_pcie_writel_apb(rockchip, val, PCIE_CLIENT_HOT_RESET_CTRL);
   469	
   470		rockchip_pcie_writel_apb(rockchip, PCIE_CLIENT_EP_MODE,
   471					 PCIE_CLIENT_GENERAL_CONTROL);
   472	
   473		rockchip->pci.ep.ops = &rockchip_pcie_ep_ops;
   474		rockchip->pci.ep.page_size = SZ_64K;
   475	
   476		dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64));
   477	
   478		ret = dw_pcie_ep_init(&rockchip->pci.ep);
   479		if (ret) {
   480			dev_err(dev, "failed to initialize endpoint\n");
   481			return ret;
   482		}
   483	
   484		ret = dw_pcie_ep_init_registers(&rockchip->pci.ep);
   485		if (ret) {
   486			dev_err(dev, "failed to initialize DWC endpoint registers\n");
   487			dw_pcie_ep_deinit(&rockchip->pci.ep);
   488			return ret;
   489		}
   490	
 > 491		pci_epc_init_notify(rockchip->pci.ep.epc);
   492	
   493		/* unmask DLL up/down indicator and hot reset/link-down reset */
   494		rockchip_pcie_writel_apb(rockchip, 0x60000, PCIE_CLIENT_INTR_MASK_MISC);
   495	
   496		return ret;
   497	}
   498	

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