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AJvYcCUEcDoDr7/KYRSjRMgpqahnp50zVqdJLw+Ce30byIvPAkt4WTthZyR/n/KWOX02XZf3aiWdqPotpsfg2RG7H7P0eP4mBaRTVLjq X-Gm-Message-State: AOJu0Yx9W0ZZU0QlEIv66OrTGJU6U8B9zOKV91fC0kcD+NLZCDMbnESU HF6jR+kcLnmU9SRZV1a6OX4J7Zht+eWmiTOZsUr6dtvyehxaVCvMrzEmJMhVXg== X-Google-Smtp-Source: AGHT+IGyfue7LPLZ7LilRGBZbjr/2wxVRS0FTY7k1T7f6sAuKaMo1GK7re9KdEfypZs3yJjqAb56XQ== X-Received: by 2002:a05:6a21:18d:b0:1be:bff2:b1b0 with SMTP id adf61e73a8af0-1bef620cb64mr6541664637.40.1719763453270; Sun, 30 Jun 2024 09:04:13 -0700 (PDT) Received: from thinkpad ([220.158.156.215]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1fac11d8b18sm47987155ad.99.2024.06.30.09.04.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 30 Jun 2024 09:04:12 -0700 (PDT) Date: Sun, 30 Jun 2024 21:34:04 +0530 From: Manivannan Sadhasivam To: Frank Li Cc: Richard Zhu , Lucas Stach , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Philipp Zabel , Liam Girdwood , Mark Brown , Krzysztof Kozlowski , Conor Dooley , linux-pci@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, bpf@vger.kernel.org, devicetree@vger.kernel.org Subject: Re: [PATCH v6 04/10] PCI: imx6: Introduce SoC specific callbacks for controlling REFCLK Message-ID: <20240630160404.GA5264@thinkpad> References: <20240617-pci2_upstream-v6-0-e0821238f997@nxp.com> <20240617-pci2_upstream-v6-4-e0821238f997@nxp.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20240617-pci2_upstream-v6-4-e0821238f997@nxp.com> On Mon, Jun 17, 2024 at 04:16:40PM -0400, Frank Li wrote: > Instead of using the switch case statement to enable/disable the reference > clock handled by this driver itself, let's introduce a new callback > set_ref_clk() and define it for platforms that require it. This simplifies Should this be called 'enable_ref_clk' since the callback is supposed to enable REFCLK? > the code. > > Signed-off-by: Frank Li > --- > drivers/pci/controller/dwc/pci-imx6.c | 112 ++++++++++++++++------------------ > 1 file changed, 52 insertions(+), 60 deletions(-) > > diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c > index 47134e2dfecf2..ff9d0098294fa 100644 > --- a/drivers/pci/controller/dwc/pci-imx6.c > +++ b/drivers/pci/controller/dwc/pci-imx6.c > @@ -103,6 +103,7 @@ struct imx_pcie_drvdata { > const u32 mode_mask[IMX_PCIE_MAX_INSTANCES]; > const struct pci_epc_features *epc_features; > int (*init_phy)(struct imx_pcie *pcie); > + int (*set_ref_clk)(struct imx_pcie *pcie, bool enable); > }; > > struct imx_pcie { > @@ -585,21 +586,19 @@ static int imx_pcie_attach_pd(struct device *dev) > return 0; > } > > -static int imx_pcie_enable_ref_clk(struct imx_pcie *imx_pcie) > +static int imx6sx_pcie_set_ref_clk(struct imx_pcie *imx_pcie, bool enable) > { > - unsigned int offset; > - int ret = 0; > + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, IMX6SX_GPR12_PCIE_TEST_POWERDOWN, > + enable ? 0 : IMX6SX_GPR12_PCIE_TEST_POWERDOWN); > > - switch (imx_pcie->drvdata->variant) { > - case IMX6SX: > - regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, > - IMX6SX_GPR12_PCIE_TEST_POWERDOWN, 0); > - break; > - case IMX6QP: > - case IMX6Q: > + return 0; > +} > + > +static int imx6q_pcie_set_ref_clk(struct imx_pcie *imx_pcie, bool enable) > +{ > + if (enable) { > /* power up core phy and enable ref clock */ > - regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, > - IMX6Q_GPR1_PCIE_TEST_PD, 0 << 18); > + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_TEST_PD, 0); > /* > * the async reset input need ref clock to sync internally, > * when the ref clock comes after reset, internal synced > @@ -608,54 +607,34 @@ static int imx_pcie_enable_ref_clk(struct imx_pcie *imx_pcie) > */ > usleep_range(10, 100); > regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, > - IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16); > - break; > - case IMX7D: > - case IMX95: > - case IMX95_EP: > - break; > - case IMX8MM: > - case IMX8MM_EP: > - case IMX8MQ: > - case IMX8MQ_EP: > - case IMX8MP: > - case IMX8MP_EP: > - offset = imx_pcie_grp_offset(imx_pcie); > - /* > - * Set the over ride low and enabled > - * make sure that REF_CLK is turned on. > - */ > - regmap_update_bits(imx_pcie->iomuxc_gpr, offset, > - IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE, > - 0); > - regmap_update_bits(imx_pcie->iomuxc_gpr, offset, > - IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN, > - IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN); > - break; > + IMX6Q_GPR1_PCIE_REF_CLK_EN, IMX6Q_GPR1_PCIE_REF_CLK_EN); > + } else { > + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, > + IMX6Q_GPR1_PCIE_REF_CLK_EN, 0); > + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, > + IMX6Q_GPR1_PCIE_TEST_PD, IMX6Q_GPR1_PCIE_TEST_PD); > } > > - return ret; > + return 0; > } > > -static void imx_pcie_disable_ref_clk(struct imx_pcie *imx_pcie) > +static int imx8mm_pcie_set_ref_clk(struct imx_pcie *imx_pcie, bool enable) > { > - switch (imx_pcie->drvdata->variant) { > - case IMX6QP: > - case IMX6Q: > - regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, > - IMX6Q_GPR1_PCIE_REF_CLK_EN, 0); > - regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, > - IMX6Q_GPR1_PCIE_TEST_PD, > - IMX6Q_GPR1_PCIE_TEST_PD); > - break; > - case IMX7D: > - regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, > - IMX7D_GPR12_PCIE_PHY_REFCLK_SEL, > - IMX7D_GPR12_PCIE_PHY_REFCLK_SEL); > - break; > - default: > - break; > - } > + int offset = imx_pcie_grp_offset(imx_pcie); > + > + /* Set the over ride low and enabled make sure that REF_CLK is turned on.*/ This comment provides no useful info. So please remove it. > + regmap_update_bits(imx_pcie->iomuxc_gpr, offset, IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE, > + enable ? 0 : IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE); > + regmap_update_bits(imx_pcie->iomuxc_gpr, offset, IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN, > + enable ? IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN : 0); > + return 0; > +} > + > +static int imx7d_pcie_set_ref_clk(struct imx_pcie *imx_pcie, bool enable) > +{ > + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, IMX7D_GPR12_PCIE_PHY_REFCLK_SEL, > + enable ? 0 : IMX7D_GPR12_PCIE_PHY_REFCLK_SEL); > + return 0; Previously imx6_pcie_enable_ref_clk() was bailing out for IMX7D. But now you are explicitly enabling it. What is the reason? - Mani -- மணிவண்ணன் சதாசிவம்