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AJvYcCVZhlxv5PMxnKhVx5jB0TKkvchNicUUNBiNR232frIbUeIXMmgYA7PlQI/+FhjIapLgZ4ohE17vHQQ9L9xa0R8vSSfaIOEeqqBB X-Gm-Message-State: AOJu0YzBcBtaHEotfo6eTXKlFcVQwRRZRLgEspyOmJ9waoGyT6JZCZoD EHcri9IRbfG+tdI4835rradOhuq6zn3v9UmGs+j9z5UhP4wGHUIKdwizc57asw== X-Google-Smtp-Source: AGHT+IFfjJ8Cc595RCoBIrmV7WXBKOr6HnF25bvKEhlw/SDpWj45/smT1TJlSOniO5oPcyQREg2Jnw== X-Received: by 2002:a05:6830:3986:b0:704:4808:1d7a with SMTP id 46e09a7af769-708fdb22d04mr6996262a34.13.1721550225266; Sun, 21 Jul 2024 01:23:45 -0700 (PDT) Received: from thinkpad ([120.56.206.118]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-70cff59e188sm3520618b3a.157.2024.07.21.01.23.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 21 Jul 2024 01:23:44 -0700 (PDT) Date: Sun, 21 Jul 2024 13:53:36 +0530 From: Manivannan Sadhasivam To: Frank Li Cc: Richard Zhu , Lucas Stach , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Philipp Zabel , Liam Girdwood , Mark Brown , Krzysztof Kozlowski , Conor Dooley , linux-pci@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, bpf@vger.kernel.org, devicetree@vger.kernel.org Subject: Re: [PATCH v7 10/10] PCI: imx6: Add i.MX8Q PCIe root complex (RC) support Message-ID: <20240721082336.GG1908@thinkpad> References: <20240708-pci2_upstream-v7-0-ac00b8174f89@nxp.com> <20240708-pci2_upstream-v7-10-ac00b8174f89@nxp.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20240708-pci2_upstream-v7-10-ac00b8174f89@nxp.com> On Mon, Jul 08, 2024 at 01:08:14PM -0400, Frank Li wrote: > From: Richard Zhu > > Implement i.MX8Q (i.MX8QM, i.MX8QXP, and i.MX8DXL) PCIe RC support. While > the controller resembles that of iMX8MP, the PHY differs significantly. > Notably, there's a distinction between PCI bus addresses and CPU addresses. > > Introduce IMX_PCIE_FLAG_CPU_ADDR_FIXUP in drvdata::flags to indicate driver > need the cpu_addr_fixup() callback to facilitate CPU address to PCI bus > address conversion according to "ranges" property. > > Signed-off-by: Richard Zhu > Signed-off-by: Frank Li Reviewed-by: Manivannan Sadhasivam One comment below. > --- > drivers/pci/controller/dwc/pci-imx6.c | 35 +++++++++++++++++++++++++++++++++++ > 1 file changed, 35 insertions(+) > > diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c > index c72c7a0b0e02d..4e029d1c284e8 100644 > --- a/drivers/pci/controller/dwc/pci-imx6.c > +++ b/drivers/pci/controller/dwc/pci-imx6.c > @@ -66,6 +66,7 @@ enum imx_pcie_variants { > IMX8MQ, > IMX8MM, > IMX8MP, > + IMX8Q, > IMX95, > IMX8MQ_EP, > IMX8MM_EP, > @@ -81,6 +82,7 @@ enum imx_pcie_variants { > #define IMX_PCIE_FLAG_HAS_PHY_RESET BIT(5) > #define IMX_PCIE_FLAG_HAS_SERDES BIT(6) > #define IMX_PCIE_FLAG_SUPPORT_64BIT BIT(7) > +#define IMX_PCIE_FLAG_CPU_ADDR_FIXUP BIT(8) > > #define imx_check_flag(pci, val) (pci->drvdata->flags & val) > > @@ -1015,6 +1017,22 @@ static void imx_pcie_host_exit(struct dw_pcie_rp *pp) > regulator_disable(imx_pcie->vpcie); > } > > +static u64 imx_pcie_cpu_addr_fixup(struct dw_pcie *pcie, u64 cpu_addr) > +{ > + struct imx_pcie *imx_pcie = to_imx_pcie(pcie); > + struct dw_pcie_rp *pp = &pcie->pp; > + struct resource_entry *entry; > + unsigned int offset; > + > + if (!(imx_pcie->drvdata->flags & IMX_PCIE_FLAG_CPU_ADDR_FIXUP)) > + return cpu_addr; > + > + entry = resource_list_first_type(&pp->bridge->windows, IORESOURCE_MEM); > + offset = entry->offset; > + > + return (cpu_addr - offset); > +} > + > static const struct dw_pcie_host_ops imx_pcie_host_ops = { > .init = imx_pcie_host_init, > .deinit = imx_pcie_host_exit, > @@ -1023,6 +1041,7 @@ static const struct dw_pcie_host_ops imx_pcie_host_ops = { > static const struct dw_pcie_ops dw_pcie_ops = { > .start_link = imx_pcie_start_link, > .stop_link = imx_pcie_stop_link, > + .cpu_addr_fixup = imx_pcie_cpu_addr_fixup, > }; > > static void imx_pcie_ep_init(struct dw_pcie_ep *ep) > @@ -1452,6 +1471,13 @@ static int imx_pcie_probe(struct platform_device *pdev) > if (ret < 0) > return ret; > > + if (imx_check_flag(imx_pcie, IMX_PCIE_FLAG_CPU_ADDR_FIXUP)) { > + if (!resource_list_first_type(&pci->pp.bridge->windows, IORESOURCE_MEM)) { > + dw_pcie_host_deinit(&pci->pp); > + return dev_err_probe(dev, -ENODEV, "DTS Miss PCI memory range"); > + } Is this check really necessary? Can the driver work if there is no MEM region defined in DT (irrespective of the flag)? I can understand your intentions, but this check seems pointless to me. - Mani -- மணிவண்ணன் சதாசிவம்