[PATCH v2 0/2] Add support for Xilinx XDMA Soft IP as Root Port

[PATCH v2 0/2] Add support for Xilinx XDMA Soft IP as Root Port

[Thippeswamy Havalige]

This series of patch add support for Xilinx QDMA Soft IP as Root Port.

The Xilinx QDMA Soft IP support's 32 bit and 64bit BAR's.
As Root Port it supports MSI and legacy interrupts.

Thippeswamy Havalige (2):
  dt-bindings: PCI: xilinx-xdma: Add schemas for Xilinx QDMA PCIe Root
    Port Bridge
  PCI: xilinx-xdma: Add Xilinx QDMA Root Port driver

 .../bindings/pci/xlnx,xdma-host.yaml          | 41 ++++++++++++-
 drivers/pci/controller/pcie-xilinx-dma-pl.c   | 58 ++++++++++++++++++-
 2 files changed, 94 insertions(+), 5 deletions(-)

-- 
2.25.1

[PATCH v2 1/2] dt-bindings: PCI: xilinx-xdma: Add schemas for Xilinx QDMA PCIe Root Port Bridge

[Thippeswamy Havalige]

Add YAML devicetree schemas for Xilinx QDMA Soft IP PCIe Root Port Bridge.

Signed-off-by: Thippeswamy Havalige <thippesw@amd.com>
---
 .../bindings/pci/xlnx,xdma-host.yaml          | 41 ++++++++++++++++++-
 1 file changed, 39 insertions(+), 2 deletions(-)
---
changes in v2
- update dt node label with pcie.
---
diff --git a/Documentation/devicetree/bindings/pci/xlnx,xdma-host.yaml b/Documentation/devicetree/bindings/pci/xlnx,xdma-host.yaml
index 2f59b3a73dd2..28d9350a7fb4 100644
--- a/Documentation/devicetree/bindings/pci/xlnx,xdma-host.yaml
+++ b/Documentation/devicetree/bindings/pci/xlnx,xdma-host.yaml
@@ -14,10 +14,21 @@ allOf:
 
 properties:
   compatible:
-    const: xlnx,xdma-host-3.00
+    enum:
+      - xlnx,xdma-host-3.00
+      - xlnx,qdma-host-3.00
 
   reg:
-    maxItems: 1
+    items:
+      - description: configuration region and XDMA bridge register.
+      - description: QDMA bridge register.
+    minItems: 1
+
+  reg-names:
+    items:
+      - const: cfg
+      - const: breg
+    minItems: 1
 
   ranges:
     maxItems: 2
@@ -111,4 +122,30 @@ examples:
                 interrupt-controller;
             };
         };
+
+        pcie@80000000 {
+            compatible = "xlnx,qdma-host-3.00";
+            reg = <0x0 0x80000000 0x0 0x10000000>, <0x0 0x90000000 0x0 0x10000000>;
+            reg-names = "cfg", "breg";
+            ranges = <0x2000000 0x0 0xa8000000 0x0 0xa8000000 0x0 0x8000000>,
+                     <0x43000000 0x4 0x80000000 0x4 0x80000000 0x0 0x40000000>;
+            #address-cells = <3>;
+            #size-cells = <2>;
+            #interrupt-cells = <1>;
+            device_type = "pci";
+            interrupt-parent = <&gic>;
+            interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
+                         <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+            interrupt-names = "misc", "msi0", "msi1";
+            interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+            interrupt-map = <0 0 0 1 &pcie_intc_0 0>,
+                            <0 0 0 2 &pcie_intc_0 1>,
+                            <0 0 0 3 &pcie_intc_0 2>,
+                            <0 0 0 4 &pcie_intc_0 3>;
+            pcie_intc_1: interrupt-controller {
+                #address-cells = <0>;
+                #interrupt-cells = <1>;
+                interrupt-controller;
+            };
+        };
     };
-- 
2.25.1

[PATCH v2 2/2] PCI: xilinx-xdma: Add Xilinx QDMA Root Port driver

[Thippeswamy Havalige]

Add support for Xilinx QDMA Soft IP core as Root Port.

The versal prime devices support QDMA soft IP module in
programmable logic.

The integrated QDMA Soft IP block has integrated bridge function that
can act as PCIe Root Port.

Signed-off-by: Thippeswamy Havalige <thippesw@amd.com>
---
 drivers/pci/controller/pcie-xilinx-dma-pl.c | 58 +++++++++++++++++++--
 1 file changed, 55 insertions(+), 3 deletions(-)
---
changes in v2:
- Add description for struct pl_dma_pcie
---
diff --git a/drivers/pci/controller/pcie-xilinx-dma-pl.c b/drivers/pci/controller/pcie-xilinx-dma-pl.c
index 5be5dfd8398f..933be090f92d 100644
--- a/drivers/pci/controller/pcie-xilinx-dma-pl.c
+++ b/drivers/pci/controller/pcie-xilinx-dma-pl.c
@@ -13,6 +13,7 @@
 #include <linux/msi.h>
 #include <linux/of_address.h>
 #include <linux/of_pci.h>
+#include <linux/of_platform.h>
 
 #include "../pci.h"
 #include "pcie-xilinx-common.h"
@@ -71,10 +72,24 @@
 
 /* Phy Status/Control Register definitions */
 #define XILINX_PCIE_DMA_REG_PSCR_LNKUP	BIT(11)
+#define QDMA_BRIDGE_BASE_OFF		0xCD8
 
 /* Number of MSI IRQs */
 #define XILINX_NUM_MSI_IRQS	64
 
+enum xilinx_pl_dma_version {
+	XDMA,
+	QDMA,
+};
+
+/**
+ * struct xilinx_pl_dma_variant - PL DMA PCIe variant information
+ * @version: DMA version
+ */
+struct xilinx_pl_dma_variant {
+	enum xilinx_pl_dma_version version;
+};
+
 struct xilinx_msi {
 	struct irq_domain	*msi_domain;
 	unsigned long		*bitmap;
@@ -88,6 +103,7 @@ struct xilinx_msi {
  * struct pl_dma_pcie - PCIe port information
  * @dev: Device pointer
  * @reg_base: IO Mapped Register Base
+ * @cfg_base: IO Mapped Configuration Base
  * @irq: Interrupt number
  * @cfg: Holds mappings of config space window
  * @phys_reg_base: Physical address of reg base
@@ -97,10 +113,12 @@ struct xilinx_msi {
  * @msi: MSI information
  * @intx_irq: INTx error interrupt number
  * @lock: Lock protecting shared register access
+ * @variant: PL DMA PCIe version check pointer
  */
 struct pl_dma_pcie {
 	struct device			*dev;
 	void __iomem			*reg_base;
+	void __iomem			*cfg_base;
 	int				irq;
 	struct pci_config_window	*cfg;
 	phys_addr_t			phys_reg_base;
@@ -110,16 +128,23 @@ struct pl_dma_pcie {
 	struct xilinx_msi		msi;
 	int				intx_irq;
 	raw_spinlock_t			lock;
+	const struct xilinx_pl_dma_variant   *variant;
 };
 
 static inline u32 pcie_read(struct pl_dma_pcie *port, u32 reg)
 {
-	return readl(port->reg_base + reg);
+	if (port->variant->version == XDMA)
+		return readl(port->reg_base + reg);
+	else
+		return readl(port->reg_base + reg + QDMA_BRIDGE_BASE_OFF);
 }
 
 static inline void pcie_write(struct pl_dma_pcie *port, u32 val, u32 reg)
 {
-	writel(val, port->reg_base + reg);
+	if (port->variant->version == XDMA)
+		writel(val, port->reg_base + reg);
+	else
+		writel(val, port->reg_base + reg + QDMA_BRIDGE_BASE_OFF);
 }
 
 static inline bool xilinx_pl_dma_pcie_link_up(struct pl_dma_pcie *port)
@@ -173,7 +198,10 @@ static void __iomem *xilinx_pl_dma_pcie_map_bus(struct pci_bus *bus,
 	if (!xilinx_pl_dma_pcie_valid_device(bus, devfn))
 		return NULL;
 
-	return port->reg_base + PCIE_ECAM_OFFSET(bus->number, devfn, where);
+	if (port->variant->version == XDMA)
+		return port->reg_base + PCIE_ECAM_OFFSET(bus->number, devfn, where);
+	else
+		return port->cfg_base + PCIE_ECAM_OFFSET(bus->number, devfn, where);
 }
 
 /* PCIe operations */
@@ -731,6 +759,15 @@ static int xilinx_pl_dma_pcie_parse_dt(struct pl_dma_pcie *port,
 
 	port->reg_base = port->cfg->win;
 
+	if (port->variant->version == QDMA) {
+		port->cfg_base = port->cfg->win;
+		res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "breg");
+		port->reg_base = devm_ioremap_resource(dev, res);
+		if (IS_ERR(port->reg_base))
+			return PTR_ERR(port->reg_base);
+		port->phys_reg_base = res->start;
+	}
+
 	err = xilinx_request_msi_irq(port);
 	if (err) {
 		pci_ecam_free(port->cfg);
@@ -760,6 +797,8 @@ static int xilinx_pl_dma_pcie_probe(struct platform_device *pdev)
 	if (!bus)
 		return -ENODEV;
 
+	port->variant = of_device_get_match_data(dev);
+
 	err = xilinx_pl_dma_pcie_parse_dt(port, bus->res);
 	if (err) {
 		dev_err(dev, "Parsing DT failed\n");
@@ -791,9 +830,22 @@ static int xilinx_pl_dma_pcie_probe(struct platform_device *pdev)
 	return err;
 }
 
+static const struct xilinx_pl_dma_variant xdma_host = {
+	.version = XDMA,
+};
+
+static const struct xilinx_pl_dma_variant qdma_host = {
+	.version = QDMA,
+};
+
 static const struct of_device_id xilinx_pl_dma_pcie_of_match[] = {
 	{
 		.compatible = "xlnx,xdma-host-3.00",
+		.data = &xdma_host,
+	},
+	{
+		.compatible = "xlnx,qdma-host-3.00",
+		.data = &qdma_host,
 	},
 	{}
 };
-- 
2.25.1

Re: [PATCH v2 1/2] dt-bindings: PCI: xilinx-xdma: Add schemas for Xilinx QDMA PCIe Root Port Bridge

[Conor Dooley]

[-- Attachment #1: Type: text/plain, Size: 2798 bytes --]

On Mon, Jul 22, 2024 at 11:55:57AM +0530, Thippeswamy Havalige wrote:
> Add YAML devicetree schemas for Xilinx QDMA Soft IP PCIe Root Port Bridge.
> 
> Signed-off-by: Thippeswamy Havalige <thippesw@amd.com>
> ---
>  .../bindings/pci/xlnx,xdma-host.yaml          | 41 ++++++++++++++++++-
>  1 file changed, 39 insertions(+), 2 deletions(-)
> ---
> changes in v2
> - update dt node label with pcie.
> ---
> diff --git a/Documentation/devicetree/bindings/pci/xlnx,xdma-host.yaml b/Documentation/devicetree/bindings/pci/xlnx,xdma-host.yaml
> index 2f59b3a73dd2..28d9350a7fb4 100644
> --- a/Documentation/devicetree/bindings/pci/xlnx,xdma-host.yaml
> +++ b/Documentation/devicetree/bindings/pci/xlnx,xdma-host.yaml
> @@ -14,10 +14,21 @@ allOf:
>  
>  properties:
>    compatible:
> -    const: xlnx,xdma-host-3.00
> +    enum:
> +      - xlnx,xdma-host-3.00
> +      - xlnx,qdma-host-3.00
>  
>    reg:
> -    maxItems: 1
> +    items:
> +      - description: configuration region and XDMA bridge register.
> +      - description: QDMA bridge register.

Please constrain the new entry to only the new compatible.

> +    minItems: 1
> +
> +  reg-names:
> +    items:
> +      - const: cfg
> +      - const: breg
> +    minItems: 1
>  
>    ranges:
>      maxItems: 2
> @@ -111,4 +122,30 @@ examples:
>                  interrupt-controller;
>              };
>          };
> +
> +        pcie@80000000 {

tbh, don't see the point of a new example for this.

> +            compatible = "xlnx,qdma-host-3.00";
> +            reg = <0x0 0x80000000 0x0 0x10000000>, <0x0 0x90000000 0x0 0x10000000>;
> +            reg-names = "cfg", "breg";
> +            ranges = <0x2000000 0x0 0xa8000000 0x0 0xa8000000 0x0 0x8000000>,
> +                     <0x43000000 0x4 0x80000000 0x4 0x80000000 0x0 0x40000000>;
> +            #address-cells = <3>;
> +            #size-cells = <2>;
> +            #interrupt-cells = <1>;
> +            device_type = "pci";
> +            interrupt-parent = <&gic>;
> +            interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
> +                         <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
> +            interrupt-names = "misc", "msi0", "msi1";
> +            interrupt-map-mask = <0x0 0x0 0x0 0x7>;
> +            interrupt-map = <0 0 0 1 &pcie_intc_0 0>,
> +                            <0 0 0 2 &pcie_intc_0 1>,
> +                            <0 0 0 3 &pcie_intc_0 2>,
> +                            <0 0 0 4 &pcie_intc_0 3>;
> +            pcie_intc_1: interrupt-controller {
> +                #address-cells = <0>;
> +                #interrupt-cells = <1>;
> +                interrupt-controller;
> +            };
> +        };
>      };
> -- 
> 2.25.1
> 

[-- Attachment #2: signature.asc --]
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Re: [PATCH v2 2/2] PCI: xilinx-xdma: Add Xilinx QDMA Root Port driver

[Bjorn Helgaas]

On Mon, Jul 22, 2024 at 11:55:58AM +0530, Thippeswamy Havalige wrote:
> Add support for Xilinx QDMA Soft IP core as Root Port.
> 
> The versal prime devices support QDMA soft IP module in
> programmable logic.

Capitalize brand names.

> The integrated QDMA Soft IP block has integrated bridge function that
> can act as PCIe Root Port.

Rewrap to fill 75 columns.

> +#define QDMA_BRIDGE_BASE_OFF		0xCD8

Other #defines in this file user lower-case hex; please match them.

>  static inline u32 pcie_read(struct pl_dma_pcie *port, u32 reg)
>  {
> -	return readl(port->reg_base + reg);
> +	if (port->variant->version == XDMA)
> +		return readl(port->reg_base + reg);
> +	else
> +		return readl(port->reg_base + reg + QDMA_BRIDGE_BASE_OFF);
>  }
>  
>  static inline void pcie_write(struct pl_dma_pcie *port, u32 val, u32 reg)
>  {
> -	writel(val, port->reg_base + reg);
> +	if (port->variant->version == XDMA)
> +		writel(val, port->reg_base + reg);
> +	else
> +		writel(val, port->reg_base + reg + QDMA_BRIDGE_BASE_OFF);
>  }
>  
>  static inline bool xilinx_pl_dma_pcie_link_up(struct pl_dma_pcie *port)
> @@ -173,7 +198,10 @@ static void __iomem *xilinx_pl_dma_pcie_map_bus(struct pci_bus *bus,
>  	if (!xilinx_pl_dma_pcie_valid_device(bus, devfn))
>  		return NULL;
>  
> -	return port->reg_base + PCIE_ECAM_OFFSET(bus->number, devfn, where);
> +	if (port->variant->version == XDMA)
> +		return port->reg_base + PCIE_ECAM_OFFSET(bus->number, devfn, where);
> +	else
> +		return port->cfg_base + PCIE_ECAM_OFFSET(bus->number, devfn, where);

If you rework the variant tests above to use
"if (port->variant->version == QDMA)" instead, they will match the one
below, and you won't need to touch the existing code at all, e.g.,

  + if (port->variant->version == QDMA)
  +   return port->cfg_base + PCIE_ECAM_OFFSET(bus->number, devfn, where);

    return port->reg_base + PCIE_ECAM_OFFSET(bus->number, devfn, where);

>  }
>  
>  /* PCIe operations */
> @@ -731,6 +759,15 @@ static int xilinx_pl_dma_pcie_parse_dt(struct pl_dma_pcie *port,
>  
>  	port->reg_base = port->cfg->win;
>  
> +	if (port->variant->version == QDMA) {
> +		port->cfg_base = port->cfg->win;
> +		res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "breg");
> +		port->reg_base = devm_ioremap_resource(dev, res);
> +		if (IS_ERR(port->reg_base))
> +			return PTR_ERR(port->reg_base);
> +		port->phys_reg_base = res->start;
> +	}

RE: [PATCH v2 1/2] dt-bindings: PCI: xilinx-xdma: Add schemas for Xilinx QDMA PCIe Root Port Bridge

[Havalige, Thippeswamy]

Hi Conor Dooley,

> -----Original Message-----
> From: Conor Dooley <conor@kernel.org>
> Sent: Monday, July 22, 2024 10:15 PM
> To: Havalige, Thippeswamy <thippeswamy.havalige@amd.com>
> Cc: lpieralisi@kernel.org; kw@linux.com; robh@kernel.org;
> bhelgaas@google.com; krzk+dt@kernel.org; conor+dt@kernel.org; linux-
> kernel@vger.kernel.org; devicetree@vger.kernel.org; linux-
> pci@vger.kernel.org; Havalige, Thippeswamy
> <thippeswamy.havalige@amd.com>; linux-arm-kernel@lists.infradead.org;
> Simek, Michal <michal.simek@amd.com>
> Subject: Re: [PATCH v2 1/2] dt-bindings: PCI: xilinx-xdma: Add schemas for
> Xilinx QDMA PCIe Root Port Bridge
> 
> On Mon, Jul 22, 2024 at 11:55:57AM +0530, Thippeswamy Havalige wrote:
> > Add YAML devicetree schemas for Xilinx QDMA Soft IP PCIe Root Port
> Bridge.
> >
> > Signed-off-by: Thippeswamy Havalige <thippesw@amd.com>
> > ---
> >  .../bindings/pci/xlnx,xdma-host.yaml          | 41 ++++++++++++++++++-
> >  1 file changed, 39 insertions(+), 2 deletions(-)
> > ---
> > changes in v2
> > - update dt node label with pcie.
> > ---
> > diff --git a/Documentation/devicetree/bindings/pci/xlnx,xdma-host.yaml
> b/Documentation/devicetree/bindings/pci/xlnx,xdma-host.yaml
> > index 2f59b3a73dd2..28d9350a7fb4 100644
> > --- a/Documentation/devicetree/bindings/pci/xlnx,xdma-host.yaml
> > +++ b/Documentation/devicetree/bindings/pci/xlnx,xdma-host.yaml
> > @@ -14,10 +14,21 @@ allOf:
> >
> >  properties:
> >    compatible:
> > -    const: xlnx,xdma-host-3.00
> > +    enum:
> > +      - xlnx,xdma-host-3.00
> > +      - xlnx,qdma-host-3.00
> >
> >    reg:
> > -    maxItems: 1
> > +    items:
> > +      - description: configuration region and XDMA bridge register.
> > +      - description: QDMA bridge register.
> 
> Please constrain the new entry to only the new compatible.
- Thanks, I ll resend patch with required changes.
> 
> > +    minItems: 1
> > +
> > +  reg-names:
> > +    items:
> > +      - const: cfg
> > +      - const: breg
> > +    minItems: 1
> >
> >    ranges:
> >      maxItems: 2
> > @@ -111,4 +122,30 @@ examples:
> >                  interrupt-controller;
> >              };
> >          };
> > +
> > +        pcie@80000000 {
> 
> tbh, don't see the point of a new example for this.
- For this in both examples ranges properties are different. So, here I wanted to make sure that our example device tree bindings work straight forward when our reference designs are used.
> 
> > +            compatible = "xlnx,qdma-host-3.00";
> > +            reg = <0x0 0x80000000 0x0 0x10000000>, <0x0 0x90000000 0x0
> 0x10000000>;
> > +            reg-names = "cfg", "breg";
> > +            ranges = <0x2000000 0x0 0xa8000000 0x0 0xa8000000 0x0
> 0x8000000>,
> > +                     <0x43000000 0x4 0x80000000 0x4 0x80000000 0x0
> 0x40000000>;
> > +            #address-cells = <3>;
> > +            #size-cells = <2>;
> > +            #interrupt-cells = <1>;
> > +            device_type = "pci";
> > +            interrupt-parent = <&gic>;
> > +            interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 85
> IRQ_TYPE_LEVEL_HIGH>,
> > +                         <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
> > +            interrupt-names = "misc", "msi0", "msi1";
> > +            interrupt-map-mask = <0x0 0x0 0x0 0x7>;
> > +            interrupt-map = <0 0 0 1 &pcie_intc_0 0>,
> > +                            <0 0 0 2 &pcie_intc_0 1>,
> > +                            <0 0 0 3 &pcie_intc_0 2>,
> > +                            <0 0 0 4 &pcie_intc_0 3>;
> > +            pcie_intc_1: interrupt-controller {
> > +                #address-cells = <0>;
> > +                #interrupt-cells = <1>;
> > +                interrupt-controller;
> > +            };
> > +        };
> >      };
> > --
> > 2.25.1
> >

Regards,
Thippeswamy H

RE: [PATCH v2 2/2] PCI: xilinx-xdma: Add Xilinx QDMA Root Port driver

[Havalige, Thippeswamy]

Hi Bjorn,

Thanks, will update all your review comments and resend patch.

Regards,
Thippeswamy H

> -----Original Message-----
> From: Bjorn Helgaas <helgaas@kernel.org>
> Sent: Tuesday, July 23, 2024 3:45 AM
> To: Havalige, Thippeswamy <thippeswamy.havalige@amd.com>
> Cc: lpieralisi@kernel.org; kw@linux.com; robh@kernel.org;
> bhelgaas@google.com; krzk+dt@kernel.org; conor+dt@kernel.org; linux-
> kernel@vger.kernel.org; devicetree@vger.kernel.org; linux-
> pci@vger.kernel.org; Havalige, Thippeswamy
> <thippeswamy.havalige@amd.com>; linux-arm-kernel@lists.infradead.org;
> Simek, Michal <michal.simek@amd.com>
> Subject: Re: [PATCH v2 2/2] PCI: xilinx-xdma: Add Xilinx QDMA Root Port
> driver
> 
> On Mon, Jul 22, 2024 at 11:55:58AM +0530, Thippeswamy Havalige wrote:
> > Add support for Xilinx QDMA Soft IP core as Root Port.
> >
> > The versal prime devices support QDMA soft IP module in
> > programmable logic.
> 
> Capitalize brand names.
> 
> > The integrated QDMA Soft IP block has integrated bridge function that
> > can act as PCIe Root Port.
> 
> Rewrap to fill 75 columns.
> 
> > +#define QDMA_BRIDGE_BASE_OFF		0xCD8
> 
> Other #defines in this file user lower-case hex; please match them.
> 
> >  static inline u32 pcie_read(struct pl_dma_pcie *port, u32 reg)
> >  {
> > -	return readl(port->reg_base + reg);
> > +	if (port->variant->version == XDMA)
> > +		return readl(port->reg_base + reg);
> > +	else
> > +		return readl(port->reg_base + reg +
> QDMA_BRIDGE_BASE_OFF);
> >  }
> >
> >  static inline void pcie_write(struct pl_dma_pcie *port, u32 val, u32 reg)
> >  {
> > -	writel(val, port->reg_base + reg);
> > +	if (port->variant->version == XDMA)
> > +		writel(val, port->reg_base + reg);
> > +	else
> > +		writel(val, port->reg_base + reg +
> QDMA_BRIDGE_BASE_OFF);
> >  }
> >
> >  static inline bool xilinx_pl_dma_pcie_link_up(struct pl_dma_pcie *port)
> > @@ -173,7 +198,10 @@ static void __iomem
> *xilinx_pl_dma_pcie_map_bus(struct pci_bus *bus,
> >  	if (!xilinx_pl_dma_pcie_valid_device(bus, devfn))
> >  		return NULL;
> >
> > -	return port->reg_base + PCIE_ECAM_OFFSET(bus->number, devfn,
> where);
> > +	if (port->variant->version == XDMA)
> > +		return port->reg_base + PCIE_ECAM_OFFSET(bus->number,
> devfn, where);
> > +	else
> > +		return port->cfg_base + PCIE_ECAM_OFFSET(bus->number,
> devfn, where);
> 
> If you rework the variant tests above to use
> "if (port->variant->version == QDMA)" instead, they will match the one
> below, and you won't need to touch the existing code at all, e.g.,
> 
>   + if (port->variant->version == QDMA)
>   +   return port->cfg_base + PCIE_ECAM_OFFSET(bus->number, devfn,
> where);
> 
>     return port->reg_base + PCIE_ECAM_OFFSET(bus->number, devfn, where);
> 
> >  }
> >
> >  /* PCIe operations */
> > @@ -731,6 +759,15 @@ static int xilinx_pl_dma_pcie_parse_dt(struct
> pl_dma_pcie *port,
> >
> >  	port->reg_base = port->cfg->win;
> >
> > +	if (port->variant->version == QDMA) {
> > +		port->cfg_base = port->cfg->win;
> > +		res = platform_get_resource_byname(pdev,
> IORESOURCE_MEM, "breg");
> > +		port->reg_base = devm_ioremap_resource(dev, res);
> > +		if (IS_ERR(port->reg_base))
> > +			return PTR_ERR(port->reg_base);
> > +		port->phys_reg_base = res->start;
> > +	}

Re: [PATCH v2 1/2] dt-bindings: PCI: xilinx-xdma: Add schemas for Xilinx QDMA PCIe Root Port Bridge

[Conor Dooley]

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On Wed, Jul 24, 2024 at 09:30:21AM +0000, Havalige, Thippeswamy wrote:
> Hi Conor Dooley,
> 
> > -----Original Message-----
> > From: Conor Dooley <conor@kernel.org>
> > Sent: Monday, July 22, 2024 10:15 PM
> > To: Havalige, Thippeswamy <thippeswamy.havalige@amd.com>
> > Cc: lpieralisi@kernel.org; kw@linux.com; robh@kernel.org;
> > bhelgaas@google.com; krzk+dt@kernel.org; conor+dt@kernel.org; linux-
> > kernel@vger.kernel.org; devicetree@vger.kernel.org; linux-
> > pci@vger.kernel.org; Havalige, Thippeswamy
> > <thippeswamy.havalige@amd.com>; linux-arm-kernel@lists.infradead.org;
> > Simek, Michal <michal.simek@amd.com>
> > Subject: Re: [PATCH v2 1/2] dt-bindings: PCI: xilinx-xdma: Add schemas for
> > Xilinx QDMA PCIe Root Port Bridge
> > 
> > On Mon, Jul 22, 2024 at 11:55:57AM +0530, Thippeswamy Havalige wrote:
> > > Add YAML devicetree schemas for Xilinx QDMA Soft IP PCIe Root Port
> > Bridge.
> > >
> > > Signed-off-by: Thippeswamy Havalige <thippesw@amd.com>
> > > ---
> > >  .../bindings/pci/xlnx,xdma-host.yaml          | 41 ++++++++++++++++++-
> > >  1 file changed, 39 insertions(+), 2 deletions(-)
> > > ---
> > > changes in v2
> > > - update dt node label with pcie.
> > > ---
> > > diff --git a/Documentation/devicetree/bindings/pci/xlnx,xdma-host.yaml
> > b/Documentation/devicetree/bindings/pci/xlnx,xdma-host.yaml
> > > index 2f59b3a73dd2..28d9350a7fb4 100644
> > > --- a/Documentation/devicetree/bindings/pci/xlnx,xdma-host.yaml
> > > +++ b/Documentation/devicetree/bindings/pci/xlnx,xdma-host.yaml
> > > @@ -14,10 +14,21 @@ allOf:
> > >
> > >  properties:
> > >    compatible:
> > > -    const: xlnx,xdma-host-3.00
> > > +    enum:
> > > +      - xlnx,xdma-host-3.00
> > > +      - xlnx,qdma-host-3.00
> > >
> > >    reg:
> > > -    maxItems: 1
> > > +    items:
> > > +      - description: configuration region and XDMA bridge register.
> > > +      - description: QDMA bridge register.
> > 
> > Please constrain the new entry to only the new compatible.
> - Thanks, I ll resend patch with required changes.

Weird quoting btw, the - isn't needed.

> > > +    minItems: 1
> > > +
> > > +  reg-names:
> > > +    items:
> > > +      - const: cfg
> > > +      - const: breg
> > > +    minItems: 1
> > >
> > >    ranges:
> > >      maxItems: 2
> > > @@ -111,4 +122,30 @@ examples:
> > >                  interrupt-controller;
> > >              };
> > >          };
> > > +
> > > +        pcie@80000000 {
> > 
> > tbh, don't see the point of a new example for this.
> - For this in both examples ranges properties are different. So, here I wanted to make sure that our example device tree bindings work straight forward when our reference designs are used.

Different ranges properties doesn't justify a new example. They don't
exist to be copy-pasted, but rather to demonstrate usage of properties
and validate the binding.

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