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Wed, 24 Jul 2024 21:59:33 -0700 (PDT) Received: from thinkpad ([103.244.168.26]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1fed7f9e8fcsm4398215ad.249.2024.07.24.21.59.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Jul 2024 21:59:33 -0700 (PDT) Date: Thu, 25 Jul 2024 10:29:28 +0530 From: Manivannan Sadhasivam To: Jim Quinlan Cc: linux-pci@vger.kernel.org, Nicolas Saenz Julienne , Bjorn Helgaas , Lorenzo Pieralisi , Cyril Brulebois , Stanimir Varbanov , Krzysztof Kozlowski , bcm-kernel-feedback-list@broadcom.com, jim2101024@gmail.com, Florian Fainelli , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Rob Herring , "moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE" , "moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE" , open list Subject: Re: [PATCH v4 12/12] PCI: brcmstb: Enable 7712 SOCs Message-ID: <20240725045928.GL2317@thinkpad> References: <20240716213131.6036-1-james.quinlan@broadcom.com> <20240716213131.6036-13-james.quinlan@broadcom.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20240716213131.6036-13-james.quinlan@broadcom.com> On Tue, Jul 16, 2024 at 05:31:27PM -0400, Jim Quinlan wrote: > The Broadcom STB 7712 is the sibling chip of the RPi 5 (2712). > Could you please add more info about this SoC? What PCIe Gen it supports, lanes, IP revision etc... - Mani > Signed-off-by: Jim Quinlan > Reviewed-by: Stanimir Varbanov > Reviewed-by: Florian Fainelli > Tested-by: Florian Fainelli > --- > drivers/pci/controller/pcie-brcmstb.c | 20 ++++++++++++++++++++ > 1 file changed, 20 insertions(+) > > diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c > index fa5616a56383..7debb3599789 100644 > --- a/drivers/pci/controller/pcie-brcmstb.c > +++ b/drivers/pci/controller/pcie-brcmstb.c > @@ -1193,6 +1193,10 @@ static void brcm_extend_rbus_timeout(struct brcm_pcie *pcie) > const unsigned int REG_OFFSET = PCIE_RGR1_SW_INIT_1(pcie) - 8; > u32 timeout_us = 4000000; /* 4 seconds, our setting for L1SS */ > > + /* 7712 does not have this (RGR1) timer */ > + if (pcie->model == BCM7712) > + return; > + > /* Each unit in timeout register is 1/216,000,000 seconds */ > writel(216 * timeout_us, pcie->base + REG_OFFSET); > } > @@ -1664,6 +1668,13 @@ static const int pcie_offsets_bmips_7425[] = { > [PCIE_INTR2_CPU_BASE] = 0x4300, > }; > > +static const int pcie_offset_bcm7712[] = { > + [EXT_CFG_INDEX] = 0x9000, > + [EXT_CFG_DATA] = 0x9004, > + [PCIE_HARD_DEBUG] = 0x4304, > + [PCIE_INTR2_CPU_BASE] = 0x4400, > +}; > + > static const struct pcie_cfg_data generic_cfg = { > .offsets = pcie_offsets, > .model = GENERIC, > @@ -1729,6 +1740,14 @@ static const struct pcie_cfg_data bcm7216_cfg = { > .num_inbound = 3, > }; > > +static const struct pcie_cfg_data bcm7712_cfg = { > + .offsets = pcie_offset_bcm7712, > + .perst_set = brcm_pcie_perst_set_7278, > + .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic, > + .model = BCM7712, > + .num_inbound = 10, > +}; > + > static const struct of_device_id brcm_pcie_match[] = { > { .compatible = "brcm,bcm2711-pcie", .data = &bcm2711_cfg }, > { .compatible = "brcm,bcm4908-pcie", .data = &bcm4908_cfg }, > @@ -1738,6 +1757,7 @@ static const struct of_device_id brcm_pcie_match[] = { > { .compatible = "brcm,bcm7445-pcie", .data = &generic_cfg }, > { .compatible = "brcm,bcm7435-pcie", .data = &bcm7435_cfg }, > { .compatible = "brcm,bcm7425-pcie", .data = &bcm7425_cfg }, > + { .compatible = "brcm,bcm7712-pcie", .data = &bcm7712_cfg }, > {}, > }; > > -- > 2.17.1 > -- மணிவண்ணன் சதாசிவம்