From: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
To: Jim Quinlan <james.quinlan@broadcom.com>
Cc: linux-pci@vger.kernel.org,
"Nicolas Saenz Julienne" <nsaenz@kernel.org>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Lorenzo Pieralisi" <lorenzo.pieralisi@arm.com>,
"Cyril Brulebois" <kibi@debian.org>,
"Stanimir Varbanov" <svarbanov@suse.de>,
"Krzysztof Kozlowski" <krzk@kernel.org>,
bcm-kernel-feedback-list@broadcom.com, jim2101024@gmail.com,
"Florian Fainelli" <florian.fainelli@broadcom.com>,
"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
"Krzysztof Wilczyński" <kw@linux.com>,
"Rob Herring" <robh@kernel.org>,
"moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE"
<linux-rpi-kernel@lists.infradead.org>,
"moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE"
<linux-arm-kernel@lists.infradead.org>,
"open list" <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v4 09/12] PCI: brcmstb: Refactor for chips with many regular inbound BARs
Date: Fri, 26 Jul 2024 10:38:05 +0530 [thread overview]
Message-ID: <20240726050805.GC2628@thinkpad> (raw)
In-Reply-To: <CA+-6iNyQ09BESbdCwY1x4yUOLmAHKFBU3-9TO_ST+2GkOEEAng@mail.gmail.com>
On Thu, Jul 25, 2024 at 04:29:56PM -0400, Jim Quinlan wrote:
> On Thu, Jul 25, 2024 at 12:53 AM Manivannan Sadhasivam
> <manivannan.sadhasivam@linaro.org> wrote:
> >
> > On Tue, Jul 16, 2024 at 05:31:24PM -0400, Jim Quinlan wrote:
> > > Previously, our chips provided three inbound "BARS" with fixed purposes:
> > > the first was for mapping SoC internal registers, the second was for
> > > memory, and the third was for memory but with the endian swapped. We
> > > typically only used one of these BARs.
> > >
> > > Complicating that BARs usage was the fact that the PCIe HW would do a
> > > baroque internal mapping of system memory, and concatenate the regions of
> > > multiple memory controllers.
> > >
> > > Newer chips such as the 7712 and Cable Modem SOCs have taken a step forward
> > > and now provide multiple inbound BARs. This works in concert with the
> > > dma-ranges property, where each provided range becomes an inbound BAR.
> > >
> > > This commit provides support for these new chips and their multiple
> > > inbound BARs but also keeps the legacy support for the older system.
> > >
> >
> > BAR belongs to the endpoints not to the RC. How can the RC have 'BARs'? RC can
> > only map endpoint BARs to MEM region. What you are referring to is 'MEM region'
> > maybe?
>
> Agreed, it is confusing. Long story short, the HW team gave the
> inbound windows the label "BAR". We will still have to use their
> register names,
Wow, such an inventive naming :)
> e.g. PCIE_MISC_RC_BAR4_CONFIG_LO, but what I can do is change
> for example "struct rc_bar" to "struct inbound_win" as well as make similar
> changes to the code and function names.
>
> Let's assume you will be okay with my plan above; if not, please tell
> me what you would prefer.
>
Yes please. Just keep BAR in the register name and use 'inbound_win' elsewhere.
Even better, add a comment at the top of these register names to clarify that
these refer to inbound windows.
- Mani
--
மணிவண்ணன் சதாசிவம்
next prev parent reply other threads:[~2024-07-26 5:08 UTC|newest]
Thread overview: 47+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-07-16 21:31 [PATCH v4 00/12] PCI: brcnstb: Enable STB 7712 SOC Jim Quinlan
2024-07-16 21:31 ` [PATCH v4 01/12] dt-bindings: PCI: Cleanup of brcmstb YAML and add 7712 SoC Jim Quinlan
2024-07-17 6:51 ` Krzysztof Kozlowski
2024-07-17 13:20 ` Jim Quinlan
2024-07-17 13:30 ` Krzysztof Kozlowski
2024-07-23 18:49 ` Jim Quinlan
2024-07-17 21:06 ` Florian Fainelli
2024-07-18 6:02 ` Krzysztof Kozlowski
2024-07-18 6:07 ` Krzysztof Kozlowski
2024-07-23 18:44 ` Jim Quinlan
2024-07-24 8:05 ` Krzysztof Kozlowski
2024-07-24 18:57 ` Jim Quinlan
2024-07-16 21:31 ` [PATCH v4 02/12] dt-bindings: PCI: brcmstb: Add 7712 SoC description Jim Quinlan
2024-07-17 6:52 ` Krzysztof Kozlowski
2024-07-23 21:03 ` Jim Quinlan
2024-07-24 6:02 ` Krzysztof Kozlowski
2024-07-16 21:31 ` [PATCH v4 03/12] PCI: brcmstb: Use common error handling code in brcm_pcie_probe() Jim Quinlan
2024-07-25 4:31 ` Manivannan Sadhasivam
2024-07-25 19:45 ` Jim Quinlan
2024-07-26 5:04 ` Manivannan Sadhasivam
2024-07-26 18:34 ` Jim Quinlan
2024-07-27 6:40 ` Manivannan Sadhasivam
2024-07-29 15:24 ` Jim Quinlan
2024-07-16 21:31 ` [PATCH v4 04/12] PCI: brcmstb: Use bridge reset if available Jim Quinlan
2024-07-25 4:37 ` Manivannan Sadhasivam
2024-07-16 21:31 ` [PATCH v4 05/12] PCI: brcmstb: Use swinit " Jim Quinlan
2024-07-25 4:39 ` Manivannan Sadhasivam
2024-07-29 21:49 ` Jim Quinlan
2024-07-16 21:31 ` [PATCH v4 06/12] PCI: brcmstb: PCI: brcmstb: Make HARD_DEBUG, INTR2_CPU_BASE offsets SoC-specific Jim Quinlan
2024-07-25 4:43 ` Manivannan Sadhasivam
2024-07-16 21:31 ` [PATCH v4 07/12] PCI: brcmstb: Remove two unused constants from driver Jim Quinlan
2024-07-25 4:43 ` Manivannan Sadhasivam
2024-07-16 21:31 ` [PATCH v4 08/12] PCI: brcmstb: Don't conflate the reset rescal with phy ctrl Jim Quinlan
2024-07-25 4:48 ` Manivannan Sadhasivam
2024-07-26 19:03 ` Jim Quinlan
2024-07-16 21:31 ` [PATCH v4 09/12] PCI: brcmstb: Refactor for chips with many regular inbound BARs Jim Quinlan
2024-07-25 4:53 ` Manivannan Sadhasivam
2024-07-25 20:29 ` Jim Quinlan
2024-07-26 5:08 ` Manivannan Sadhasivam [this message]
2024-07-16 21:31 ` [PATCH v4 10/12] PCI: brcmstb: Check return value of all reset_control_xxx calls Jim Quinlan
2024-07-16 21:31 ` [PATCH v4 11/12] PCI: brcmstb: Change field name from 'type' to 'model' Jim Quinlan
2024-07-25 4:58 ` Manivannan Sadhasivam
2024-07-25 20:38 ` Jim Quinlan
2024-07-26 11:29 ` Manivannan Sadhasivam
2024-07-16 21:31 ` [PATCH v4 12/12] PCI: brcmstb: Enable 7712 SOCs Jim Quinlan
2024-07-25 4:59 ` Manivannan Sadhasivam
2024-07-25 5:03 ` [PATCH v4 00/12] PCI: brcnstb: Enable STB 7712 SOC Manivannan Sadhasivam
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